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SoC片上通信结构的研究综述 被引量:2

Summary of Research on SoC Communication Architecture
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摘要 由于系统芯片中IP核数目的逐渐增大,片上通信结构逐渐成了整个SoC的性能瓶颈,基于共享总线的SoC通信结构具有无法克服的局限性,这就对传统的共享总线片上通信系统提出了严峻的挑战。文中全面综述了近些年片上通信系统方面的研究,分析了共享总线,交叉开关,点到点,片上网络NoC(Network on Chip),混合互连五种片上通信结构的优缺点,以及对整个系统芯片性能的影响.最后指出片上通信研究的方向。 With the increasing number of IP cores, the communication architecture on chip is the bottleneck for SoC performance, the shared bus on chip has some limitations that can't be solved, and these become the challenge to the traditional SoC communication architecture. This paper summarizes the SoC communication system's research and development, and analyzes five communication architectures: share bus, crossbar, point- to- point, Network on Chip, hybrid Interconnect. The paper also analyzes the performance of different architecture. At last, the research directions of SoC communication on chip are discussed.
出处 《微处理机》 2007年第3期1-5,共5页 Microprocessors
关键词 SOC 共享总线 交叉开关 点到点 片上网络 混合片上互连 SoC Shared bus Crossbar Point - to - point NoC Hybrid Interconnect on Chip
作者简介 周文彪(1979-),男,安徽黄山人,博士研究生,主研方向:SoC微体系结构设计,片上网络。
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参考文献29

  • 1Semiconductors Industry Association.International Technology Roadmap for Semiconductors,World Semiconductors[S].World Semiconductor Council.Edition,1999.
  • 2宋廷强,刘川来,李思昆,胡乃平.SoC设计中的IP核复用技术研究[J].青岛科技大学学报(自然科学版),2003,24(3):260-263. 被引量:9
  • 3葛晨阳,徐维朴,孙飞.IP复用技术的研究[J].微电子学,2002,32(4):257-260. 被引量:9
  • 4IBM Corporation.the Connect Bus Architecture[EB/OL].www.chips.ibm.com,1999.
  • 5ARM Corporation.the AMBA Specification[EB/OL].www.arm.com,1999.
  • 6Silicore Corporation.the WISHBONE System Architeeture Specificatio[OL/EB].www.silicore.com/wishbone.him,2001.
  • 7季红彬,蒋斌,魏敬和.C Bus——一个通用的SoC总线结构[J].中国集成电路,2003,12(47):32-39. 被引量:5
  • 8Luca Benini and G D Micheh.Networks on Chips:A New SoC Paradigm[J].IEEE Computer,2002(1):70-78.
  • 9Wayne Wolf.The Future of Multiprocessor systems-on-Chips[C].DAC 2004,San Diego,California,USA,2004:681~685.
  • 10T Ye,G De Micheli and L Benini.On-Chip Interconnect Communication Analysis for MPSoC[C].In DATE'2003:40-49.

二级参考文献17

  • 1Michael Keating,Pierre Bricaud. Reuse methodology manual for system-on-a-chip design[M]. Boston/Dorecht/London:Kluwer academic publishers,2000.
  • 2Han Qi, Zheng Jiang, Jia Wei. IP reusable design methodology[J]. ASIC, 2001. Proceedings 4th International Conference, 2001,756-759.
  • 3Pran Kurup,Taher Abbasi. It's the methodology,stupid![M]. Germany:Bytek Design,lnc. 1998.
  • 4Reinaldo A B,William R L. Designing systems-on-chip using cores[J]. Annual ACM IEEE Design Automation Conference, Proceedings of 37th conference on design automation,2000,420-425.
  • 5Gajski D D,Wu A C. Essential issues for IP reuse[J]. Design Automation Conference, 2000, 37-42.
  • 6Bergamaschi R,Lee W R, Bhattacharya D. Coral-automating the design of systems-on-chip using cores[J]. Custom Integrated Circuits Conference, Proceedings of the IEEE 2000,109 -112.
  • 7Cadence. The IP Reuse Evolution [Z]. Cadence design system white paper. 1999.1-7.
  • 8Reinhardt M. Implementing a migration-based IP-reuse strategy[J]. Electronics Engineer,1999
  • 9Reed D. System-chip success begins with strategy for IP reuse [Z]. Cadence, 1999.
  • 10AMBA(tm)Specification. http://www.arm.com .

共引文献18

同被引文献8

  • 1Martin G. Overview of the MPSoC Design Challenge[C]//Proc. of the 43rd Annual Design Automation Conference. [S. l.]: ACM Press, 2006.
  • 2Kumar S. A Network on Chip Architecture and Design Methodology[C]//Proc. of ISVLSI'02.[S. l.]: IEEE Press, 2002.
  • 3Hadjiat K. An FPGA Implementation of a Sealable Network-on-Chip Based on the Token Ring Concept[C]//Proc. of the 14th IEEE International Conference on Electronics, Circuits and Systems. [S. l.]: IEEE Press, 2007.
  • 4Liljeberg R Self-timed Ring Architecture for SoC Applications[C]// Proc. of IEEE International Conf. on SoC. [S, l.]: IEEE Press, 2003.
  • 5Dally W J. Virtual-channel Flow Control[C]//Proc. of the 17th Annual International Symposium on Computer Architecture. [S. l.]: IEEE Press, 1990.
  • 6Partha P. Performance Evaluation and Design Trade-offs for Network-on-Chip Interconnect Architectures[J]. IEEE Transactions on Computers, 2005, 54(8): 1025-1040.
  • 7黄国睿,张平,魏广博.多核处理器的关键技术及其发展趋势[J].计算机工程与设计,2009,30(10):2414-2418. 被引量:48
  • 8汪健,张磊,王少轩,赵忠惠,陈亚宁.多核处理器核间高速通讯架构的研究[J].电子与封装,2011,11(6):41-48. 被引量:5

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