摘要
本文提出了一种基于遗传算法的数字电路测试图形生成方法，首先把被测电路的门级描述转化为易于计算的非线性网络，然后用遗传算法找到网络能量函数的最优解，从而得到被测电路的测试集．这种方法对可测故障都能生成测试，能方便地产生多故障的测试图形，同时具有较好的并行性，易于在多处理机上实现．
A test pattern generation approach for digital circuit is presented. The approach employs genetic algorithm to generate tests for faults. The gate level description of circuit under test (CUT) is translated into a nonlinear netwrok that can be computed easily,and an improved genetic algorithm is used to find out optimal solutions of energy function of the constrained network,so the test set of CUT is obtained. The approach has many merits,such as it can generate tests for all detectable faults including multi faults,possess the characteristics of parallel processing and can be implemented on multiprocessors.
出处
《电子学报》
EI
CAS
CSCD
北大核心
1997年第4期111-113,共3页
Acta Electronica Sinica
基金
国家"八五"攻关基金
关键词
数字电路
测试生成
遗传算法
Digital circuit,Test generation,Genetic algorithm,Expert system
