摘要
电路的日益复杂和集成度的不断提高,使测试已成为集成电路设计中费用最高、难度最大的一个环节。文章主要讨论了测试中伪随机测试矢量的生成,并提出了改进其周期的办法,从而大大提高了故障的覆盖率。最后通过硬件描述语言Verilog在Quartus Ⅱ软件下进行仿真,验证了其正确性。
Nowadays, integrated circuits are becoming more and more complex and high- integrated. Testing has become a high-expenditure and most difficult tache in the design of integrated circuits. This paper mainly discusses how to generate random test vector and propose a new method to improve it＇s period. Based on the analysis, it improves the fault coverage .Simulation which uses hardware description language Verilog in the Quartus？ software environment corroborate the results.
出处
《电子与封装》
2007年第4期18-20,48,共4页
Electronics & Packaging
作者简介
刘伟（1980-），男，山东泰安人，硕士研究生，桂林电子科技大学计算机辅助测试教研室，主要研究方向为大规模数字集成电路测试。
