摘要
提出了一种高性能MCU的控制器实现结构,利用一级流水线的预取址技术实现2时钟/机器周期,利用硬布线逻辑结构和多时钟体系结构以实现指令节拍发生器的功能.与传统8051相比,其速度大大提高,并扩展了标准8051的中断系统,具有实时、高速、多中断源的特点.利用Cadence EDA工具对电路进行了仿真,仿真结果验证了设计的准确性,并成功地在A ltera的APEX20K上通过了FPGA仿真.
A high-performance microcontroller is described, in which 2-clock period per machine cycle architecture and pre-fetching instruction method of the first level pipeline technology are put forward to improve MCU＇s power efficiency. At the same time, the MCU also adopts a hard-wired control unit and multiple clock systems architecture to achieve instruction timing function. This MCU＇s speed is higher than the standard Intel 8051, successfully simulated in Cadence EDA tools and also in Altera＇ s APEX20K FPGA.
出处
《上海电力学院学报》
CAS
2006年第2期109-112,共4页
Journal of Shanghai University of Electric Power
关键词
微控制器
中断系统
多时钟体系
microcontroller
interrupt system
multiple clock system
