期刊文献+

低踢回噪声锁存比较器的分析与设计 被引量:7

Analysis and Design of a Latched Comparator with Low Kickback Noise
在线阅读 下载PDF
导出
摘要 设计了一种低踢回噪声锁存比较器,着重分析和优化了比较器的速度和失调电压。在0.35μmCMOS工艺条件下,采用Hspice对电路进行了模拟。结果表明,比较器的最高工作频率为200MHz,分辨率在6位以上,灵敏度为0.3mV;在2.5V电源电压下,功耗为70μW。 A latched comparator with low kickback noise is designed, and the speed and offset voltage of the comparator are analyzed. Simulation with Hspice in 0.35 μm CMOS technology shows that the comparator has achieved a maximum operating frequency of 200 MHz, a resolution up to 6 bits, and a sensitivity of 0.3 inV. Operating with a single 2. 5 V supply, it dissipates 70μW of power.
出处 《微电子学》 CAS CSCD 北大核心 2005年第4期428-432,共5页 Microelectronics
关键词 锁存比较器 踢回噪声 失调电压 Latched comparator Kickback noise Offset voltage
作者简介 程剑平(1977-)。男(汉族),江苏省苏州市人,博士研究生,主要研究方向为∑-△A/D转换器和D/A转换器。
  • 相关文献

参考文献12

  • 1Figueiredo P M, Vital J C. Low kickback noise techniques for CMOS latched comparators [A]. Int Symp Circ and Syst [C]. Vancouver, Canada. 2004. I-537-40.
  • 2Cusinato P, Bruccoleri M. Caviglia D D, et al. Analysis of the behavior of a dynamic latch comparator [J].IEEE Trans Circ and Syst, I: Fundamental Theory and Applications, 1998, 45(3) : 294-298.
  • 3Razavi I3, Wooley B A. Design techniques for high-speed, high-resolution comparators [J]. IEEE J .Sol Sta Circ, 1992, 27(12): 1916-1926.
  • 4Yin G M, Eynde F O, Sansen W. A high-speed CMOS comparator with 8-b resolution [J]. IEEE J Sol Sta Circ,1992,27(2) : 208-211.
  • 5John J A, Martin K. Analog integrated circuit design[M]. New York: John Wiley & Sons, Inc. 1997.
  • 6Choi M, Abidi. A 6 bit 1.3-Gsample/s flash ADC in 0.35-μm CMOS [J]. IEEE J Sol Sta Circ, 2001, 36(12): 1847-1858.
  • 7Gray P R, Hurst P J. Analysis and design of analog integrated circuits [M]. New York: John Wiley Sons, Inc. 2001.
  • 8Ho J, Cam L H. A 3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC [A]. IEEE Asia Pacific Conf Circ and Syst [C]. Seoul,Korea. 1996. 413-416.
  • 9Serrano-Gotarredona T. Linares-Barranco B, A methodology for MOS transistor mismatch parameter extraction and mismatch simulation [A]. Int Symp Circand Syst [C]. Geneva, 2000. 109-112.
  • 10Pelgrom M J M, Duinmaijer A C J, Welbers A P G,Matching properties of MOS transistors [J]. IEEE J Sol Sta Circ, 1989, 24(5): 1433-1439.

同被引文献50

引证文献7

二级引证文献10

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部