摘要
根据RS译码算法原理[1] ,结合DVB(数字视频广播 )系统中译码的具体指标要求以及芯片模块化的思想 ,通过对BM算法实现的优化和改进 ,采用FPGA技术实现了RS译码电路 ,通过了QUAR TUSII仿真测试以及试验板调试。由于采用了流水线技术、新的无求逆的BM算法以及关键环节的优化设计 ,使得该译码器速度快 ,占用资源少 ,译码速率可达 2 0Msps。
Based on RS decoding algorithm,combining with the specific requirements of the decoding module in the digital video broadcast system, also with the modularization conception, we apply FPGA technique to implement RS decoding circuit by means of optimizing and amending of BM algorithm, and we have simulated the design on QUARTUSII platform, then verified it on hardware circuits board. For pipeline structure and new non-inversion BM algorithm as well as optimized design in some key steps having been exploited, the decoder has the properties of high processing speed with 20Msps and small resource.
出处
《中国有线电视》
北大核心
2004年第19期8-11,共4页
China Digital Cable TV
基金
云南省省院省校科技合作计划资助项目 (2 0 0 3sablb0 0a0 44 )
