摘要
介绍了采用并行结构实现高速Viterbi译码器专用VLSI方面的新进展,描述了在Viterbi译码算法的不同层次上(包括比特层、字层和算法层)引入的额外并行结构,采用这些额外并行结构可以使专用VLSI实现的Viterbi译码器最高译码速率成倍增加。
The paper introduces new developments of implementing high speed Viterbi decoder VLSI with parallel structures and describes the additional parallel structures in different levels,including bit level, word level and algorithm level. By adopting these additional parallel structures, the maximun decoding rate of Viterbi decoder implemented by VLSI can be increased several times.
出处
《电信科学》
北大核心
1993年第2期45-49,共5页
Telecommunications Science
