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25~28 Gbit/s CMOS高灵敏度光接收机电路设计

Design of a 25-28 Gbit/s CMOS High Sensitive Optical Receiver
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摘要 基于65 nm CMOS工艺设计了一种25~28 Gbit/s具有自适应均衡和时钟数据恢复功能的光接收机电路。光接收前端采用低带宽设计,以优化接收机的灵敏度;采用判决反馈均衡器,以恢复低带宽前端引入的码间干扰。为了适应不同速率和工艺角引入的码间干扰,结合SS-LMS自适应算法,实现信号的自适应均衡。无参考时钟数据恢复电路采用鉴频环路拓宽频率捕获范围,同时将半速率鉴相器嵌入均衡器中,以降低功耗和成本。后仿真结果表明,在100 fF光电二极管的寄生电容条件下,接收前端最大增益达到66 dBΩ,25%带宽处的等效输入噪声电流为15.3 pA·Hz^(-1/2),光接收机灵敏度为-14.5 dBm。当电源电压为1.2 V时,光接收机的整体功耗为181.1 mW。 A 25-28 Gbit/s optical receiver circuit with adaptive equalization and clock data recovery was designed in a 65 nm CMOS technology.The analog front-end adopted a low-bandwidth design to optimize the receiver's sensitivity.A decision feedback equalizer was used to recover the inter-symbol interference(ISI)introduced by the low-bandwidth front-end.In order to adapt to the inter-symbol interference introduced by different rates and process corners,the adaptive equalization of the signal was realized by combining the SS-LMS adaptive algorithm.The reference-less clock data recovery circuit used a frequency discrimination loop to widen the frequency capture range,which embedded a half-rate phase detector(PD)in the equalizer to reduce power consumption and cost.The postsimulation results show that under the parasitic capacitance of the 100 fF photodiode,the maximum gain of the receiving front end reaches 66 dBΩ,the equivalent input noise current at 25%bandwidth is 15.3 pA·Hz^(-1/2),and the sensitivity of the optical receiver is-14.5 dBm.When the supply voltage is 1.2 V,the overall power consumption of the optical receiver is 181.1 mW.
作者 金高哲 张长春 袁丰 张瑛 张翼 JIN Gaozhe;ZHANG Changchun;YUAN Feng;ZHANG Ying;ZHANG Yi(College of Integrated Circuit Science and Engineering,Nanjing University of Posts and Telecommunications,Nanjing 210023,P.R.China;State Key Laboratory of Millimeter Waves,Southeast University,Nanjing 210096,P.R.China)
出处 《微电子学》 CAS 北大核心 2023年第4期581-587,共7页 Microelectronics
基金 国家自然科学基金资助项目(62174090) 毫米波国家重点实验室开放课题(K202325)
关键词 光接收机前端 判决反馈均衡器 时钟数据恢复电路 无参考时钟 嵌入式鉴相器 optical receiver front end decision feedback equalizer clock data recovery circuit reference-less clock embedded phase detector
作者简介 金高哲(1998—),男(汉族),浙江金华人,硕士研究生,研究方向为光通信集成电路设计;通信作者:张长春(1981—),男(汉族),河南南阳人,博士,教授,博士生导师,研究方向为有线/无线收发器及能量收集芯片设计
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