摘要
Inspired by real biological neural models,Spiking Neural Networks(SNNs)process information with discrete spikes and show great potential for building low-power neural network systems.This paper proposes a hardware implementation of SNN based on Field-Programmable Gate Arrays(FPGA).It features a hybrid updating algorithm,which combines the advantages of existing algorithms to simplify hardware design and improve performance.The proposed design supports up to 16384 neurons and 16.8 million synapses but requires minimal hardware resources and archieves a very low power consumption of 0.477 W.A test platform is built based on the proposed design using a Xilinx FPGA evaluation board,upon which we deploy a classification task on the MNIST dataset.The evaluation results show an accuracy of 97.06%and a frame rate of 161 frames per second.
Inspired by real biological neural models, Spiking Neural Networks(SNNs) process information with discrete spikes and show great potential for building low-power neural network systems.This paper proposes a hardware implementation of SNN based on Field-Programmable Gate Arrays(FPGA).It features a hybrid updating algorithm,which combines the advantages of existing algorithms to simplify hardware design and improve performance.The proposed design supports up to 16 384 neurons and 16.8 million synapses but requires minimal hardware resources and archieves a very low power consumption of 0.477 W.A test platform is built based on the proposed design using a Xilinx FPGA evaluation board, upon which we deploy a classification task on the MNIST dataset.The evaluation results show an accuracy of 97.06% and a frame rate of 161 frames per second.
基金
supported in part by the Beijing Innovation Center for Future Chip,Tsinghua University
in part by the Science and Technology Innovation Special Zone project,China
in part by the Tsinghua University Initiative Scientific Research Program(No.2018Z05JDX005).
作者简介
Jianhui Han,received the BS degree from Tsinghua University,Beijing,China,in 2016.He is currently working toward the PhD degree at the Institute of Microelectronics,Tsinghua University,Beijing,China.His main research interests include digital circuit/system design and emerging technology-based machine learning acceleration.E-mail:hanjh16@mails.tsinghua.edu.cn;Corresponding author:Zhaolin Li,received the BS and PhD degrees from Harbin Institute of Technology,Harbin,China,in 1994 and 2000,respectively.He is currently a professor with the Research Institute of Information Technology,Tsinghua University,Beijing,China.His current research interests include embedded systems,parallel computing,multicore design,and system-on-achip.Email:lzl73@mail.tsinghua.edu.cn;Weimin Zheng,received the MS degree from Tsinghua University,Beijing,China.Currently he is an Academician of Chinese Academy of Engineering and a professor at the Department of Computer Science and Technology,Tsinghua University,Beijing,China.His research interests include high performance computing,network storage,and parallel compiler.E-mail:zwm-dcs@mail.tsinghua.edu.cn;Youhui Zhang,received the BS and PhD degrees from Tsinghua University,Beijing,China,in 1998 and 2002,respectively.He is currently a professor in the Department of Computer Science and Technology,Tsinghua University,Beijing,China.His research interests include computer architecture and neuromorphic computing.He is a member of CCF,ACM,and IEEE.E-mail:zyh02@tsinghua.edu.cn
