The InGaAs/InAIAs/InP high electron mobility transistor （HEM：F） structures with lattice-matched and pseudo- morphic channels are grown by gas source molecular beam epitaxy. Effects of Si ^-doping condition and grow...The InGaAs/InAIAs/InP high electron mobility transistor （HEM：F） structures with lattice-matched and pseudo- morphic channels are grown by gas source molecular beam epitaxy. Effects of Si ^-doping condition and growth interruption on the electrical properties are investigated by changing the Si-cell temperature, doping time and growth process. It is found that the optimal Si ^-doping concentration （Nd） is about 5.0 x 1012 cm-2 and the use of growth interruption has a dramatic effect on the improvement of electrical properties. The material structure and crystal interface are analyzed by secondary ion mass spectroscopy and high resolution transmission elec- tron microscopy. An InGaAs/InAiAs/InP HEMT device with a gate length of lOOnm is fabricated. The device presents good pinch-off characteristics and the kink-effect of the device is trifling. In addition, the device exhibits fT = 249 GHa and fmax 〉 400 GHz.展开更多
Emitted multi-crystalline silicon and black silicon solar cells are conformal doped by ion implantation using the plasma immersion ion implantation （PⅢ） technique. The non-uniformity of emitter doping is lower than...Emitted multi-crystalline silicon and black silicon solar cells are conformal doped by ion implantation using the plasma immersion ion implantation （PⅢ） technique. The non-uniformity of emitter doping is lower than 5 %. The secondary ion mass spectrometer profile indicates that the PⅢ technique obtained 100-rim shallow emitter and the emitter depth could be impelled by furnace annealing to 220 nm and 330 nm at 850 ℃ with one and two hours, respectively. Furnace annealing at 850 ℃ could effectively electrically activate the dopants in the silicon. The efficiency of the black silicon solar cell is 14.84% higher than that of the mc-silicon solar cell due to more incident light being absorbed.展开更多
The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy di...The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI（90℃,125℃, 160℃） are studied and activation energy（Ea） values（0.13 eV and 0.15 eV） are extracted. Although the equivalent oxide thickness（EOT） values of two TiN thickness values are almost similar（0.85 nm and 0.87 nm）, the 2.4-nm TiN one（thicker Ti N capping layer） shows better PBTI reliability（13.41% at 0.9 V, 90℃, 1000 s）. This is due to the better interfacial layer/high-k（IL/HK） interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.展开更多
The （60）Co-γ ray total ionizing dose radiation responses of 55-nm silicon-oxide-nitride-oxide-silicon（SONOS） memory cells in pulse mode（programmed/erased with pulse voltage） and dc mode（programmed/erased with ...The （60）Co-γ ray total ionizing dose radiation responses of 55-nm silicon-oxide-nitride-oxide-silicon（SONOS） memory cells in pulse mode（programmed/erased with pulse voltage） and dc mode（programmed/erased with direct voltage sweeping） are investigated. The threshold voltage and off-state current of memory cells before and after radiation are measured. The experimental results show that the memory cells in pulse mode have a better radiation-hard capability. The normalized memory window still remains at 60% for cells in dc mode and 76% for cells in pulse mode after 300 krad（Si） radiation. The charge loss process physical mechanisms of programmed SONOS devices during radiation are analyzed.展开更多
The single-shot readout data process is essential for the realization of high-fidelity qubits and fault-tolerant quantum algorithms in semiconductor quantum dots. However, the fidelity and visibility of the readout pr...The single-shot readout data process is essential for the realization of high-fidelity qubits and fault-tolerant quantum algorithms in semiconductor quantum dots. However, the fidelity and visibility of the readout process are sensitive to the choice of the thresholds and limited by the experimental hardware. By demonstrating the linear dependence between the measured spin state probabilities and readout visibilities along with dark counts, we describe an alternative threshold-independent method for the single-shot readout of spin qubits in semiconductor quantum dots. We can obtain the extrapolated spin state probabilities of the prepared probabilities of the excited spin state through the threshold-independent method. We then analyze the corresponding errors of the method, finding that errors of the extrapolated probabilities cannot be neglected with no constraints on the readout time and threshold voltage. Therefore, by limiting the readout time and threshold voltage, we ensure the accuracy of the extrapolated probability. We then prove that the efficiency and robustness of this method are 60 times larger than those of the most commonly used method. Moreover, we discuss the influence of the electron temperature on the effective area with a fixed external magnetic field and provide a preliminary demonstration for a single-shot readout of up to 0.7K/1.5T in the future.展开更多
Valley, the intrinsic feature of silicon, is an inescapable subject in silicon-based quantum computing. At the spin–valley hotspot, both Rabi frequency and state relaxation rate are significantly enhanced. With prote...Valley, the intrinsic feature of silicon, is an inescapable subject in silicon-based quantum computing. At the spin–valley hotspot, both Rabi frequency and state relaxation rate are significantly enhanced. With protection against charge noise, the valley degree of freedom is also conceived to encode a qubit to realize noise-resistant quantum computing.Here, based on the spin qubit composed of one or three electrons, we characterize the intrinsic properties of valley in an isotopically enriched silicon quantum dot(QD) device. For one-electron qubit, we measure two electric-dipole spin resonance(EDSR) signals which are attributed to partial occupation of two valley states. The resonance frequencies of two EDSR signals have opposite electric field dependences. Moreover, we characterize the electric field dependence of the upper valley state based on three-electron qubit experiments. The difference of electric field dependences of the two valleys is 52.02 MHz/V, which is beneficial for tuning qubit frequency to meet different experimental requirements. As an extension of electrical control spin qubits, the opposite electric field dependence is crucial for qubit addressability,individual single-qubit control and two-qubit gate approaches in scalable quantum computing.展开更多
InA1As/InGaAs high electron mobility transistors （HEMTs） on an InP substrate with well-balanced cutoff frequency fT and maximum oscillation frequency frnax are reported. An InA1As/InGaAs HEMT with 100-nm gate length...InA1As/InGaAs high electron mobility transistors （HEMTs） on an InP substrate with well-balanced cutoff frequency fT and maximum oscillation frequency frnax are reported. An InA1As/InGaAs HEMT with 100-nm gate length and gate width of 2 × 50 μm shows excellent DC characteristics, including full channel current of 724 mA/mm, extrinsic maximum transconductance gm.max of 1051 mS/mm, and drain-gate breakdown voltage BVDG of 5.92 V. In addition, this device exhibits fT = 249 GHz and fmax = 415 GHz. These results were obtained by fabricating an asymmetrically recessed gate and minimizing the parasitic resistances. The specific Ohmic contact resistance was reduced to 0.031 0.mm. Moreover, the fT obtained in this work is the highest ever reported in 100-nm gate length InA1As/InGaAs InP-based HEMTs. The outstanding gm.max, fT, fmax, and good BVDG make the device suitable for applications in low noise amplifiers, power amplifiers, and high speed circuits.展开更多
A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability（PBTI） stress ...A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability（PBTI） stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.展开更多
In this study, the physics-based device simulation tool Silvaco ATLAS is used to characterize the electrical properties of an AlGaN/GaN high electron mobility transistor （HEMT） with a U-type gate foot. The U-gate Al...In this study, the physics-based device simulation tool Silvaco ATLAS is used to characterize the electrical properties of an AlGaN/GaN high electron mobility transistor （HEMT） with a U-type gate foot. The U-gate AlGaN/GaN HEMT mainly features a gradually changed sidewall angle, which effectively mitigates the electric field in the channel, thus obtaining enhanced off-state breakdown characteristics. At the same time, only a small additional gate capacitance and decreased gate resistance ensure excellent RF characteristics for the U-gate device. U-gate AlGaN/GaN HEMTs are feasible through adjusting the etching conditions of an inductively coupled plasma system, without introducing any extra process steps. The simulation results are confirmed by experimental measurements. These features indicate that U-gate A1GaN/GaN HEMTs might be promising candidates for use in millimeter-wave power applications.展开更多
During the forming process of the free-standing structure or the functional cavity when releasing the high aspect ratio sacrificial layer, such structures tend to stick to the substrate due to capillary force. This pa...During the forming process of the free-standing structure or the functional cavity when releasing the high aspect ratio sacrificial layer, such structures tend to stick to the substrate due to capillary force. This paper describes the application of pull-in length conception as design rules to a novel ＇dimpled＇ method in releasing sacrificial layer. Based on the conception of pull-in length in adhering Phenomenon, the fabrication and releasing sacrificial layer methods using micro bumps based on the silicon substrate were presented. According to the thermal isolation performances of one kind of micro electromechanical system device thermal shear stress sensor, the sacrificial layers were validated to be successfully released.展开更多
The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have hug...The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have huge demands on high integration density and low power consumption.The cross-point configuration or passive array,which offers the smallest footprint of cell size and feasible capability of multi-layer stacking,has received broad attention from the research community.In such array,correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells.This target requires nonlinear I-V characteristics of the memory cell,which can be realized by either adding separate selector or developing implicit build-in nonlinear cells.The performance of a passive array largely depends on the cell nonlinearity,reliability,on/off ratio,line resistance,thermal coupling,etc.This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration.First,the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures.Next,the state of the arts on the development of various selector devices and self-selective cells are presented.Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles.Then,the reliability issues in 3D array are summarized in terms of uniformity,endurance,retention,and disturbance.Subsequently,scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed,and applications of 3D RRAM beyond storage,such as neuromorphic computing and CMOL circuit are discussed later.Summary and outlooks are given in the final.展开更多
Since defects such as traps and oxygen vacancies exist in dielectrics,it is difficult to fabricate a high-performance MoS_(2)field-effect transistor(FET)using atomic layer deposition(ALD)Al_(2)O_(3)as the gate dielect...Since defects such as traps and oxygen vacancies exist in dielectrics,it is difficult to fabricate a high-performance MoS_(2)field-effect transistor(FET)using atomic layer deposition(ALD)Al_(2)O_(3)as the gate dielectric layer.In this paper,NH_(3)in situ doping,a process treatment approach during ALD growth of Al_(2)O_(3),is used to decrease these defects for better device characteristics.MoS_(2)FET has been well fabricated with this technique and the effect of different NH_(3)in situ doping sequences in the growth cycle has been investigated in detail.Compared with counterparts,those devices with NH_(3)in situ doping demonstrate obvious performance enhancements:Ion/Ioff is improved by one order of magnitude,from 1.33×10^(5)to 3.56×10^(6),the threshold voltage shifts from-0.74 V to-0.12 V and a small subthreshold swing of 105 m V/dec is achieved.The improved MoS_(2)FET performance is attributed to nitrogen doping by the introduction of NH_(3)during the Al_(2)O_(3)ALD growth process,which leads to a reduction in the surface roughness of the dielectric layer and the repair of oxygen vacancies in the Al_(2)O_(3)layer.Furthermore,the MoS_(2)FET processed by in situ NH_(3)doping after the Al and O precursor filling cycles demonstrates the best performance;this may be because the final NH_(3)doping after film growth restores more oxygen vacancies to screen more charge scattering in the MoS_(2)channel.The reported method provides a promising way to reduce charge scattering in carrier transport for high-performance MoS_(2)devices.展开更多
A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. ...A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.展开更多
A promising technology named epitaxy on nano-scale freestanding fin （ENFF） is firstly proposed for hetero- epitaxy. This technology can effectively release total strain energy and then can reduce the probability of ...A promising technology named epitaxy on nano-scale freestanding fin （ENFF） is firstly proposed for hetero- epitaxy. This technology can effectively release total strain energy and then can reduce the probability of gener- ating mismatch dislocations. Based on the calculation, dislocation defects can be eliminated completely when the thickness of the Si freestanding fin is less than 10nm for the epitaxial Ge layer. In addition, this proposed ENFF process can provide sufficient uniaxial stress for the epitaxy layer, which can be the major stressor for the SiGe or Ge channel fin field-effect transistor or nanowire at the 10nm node and beyond. According to the results of technology computer-aided design simulation, nanowires integrated with ENFF show excellent electrical perfor- mance for uniaxial stress and band offset. The ENFF process is compatible with the state of the art mainstream technology, which has a good potential for future applications.展开更多
Normal-incidence transmission measurements are commonly used for determining the real part of the in-plane optical conductivities σ1 （ω） of graphene layers. We present an accurate expression for σ1 （ω） in a cl...Normal-incidence transmission measurements are commonly used for determining the real part of the in-plane optical conductivities σ1 （ω） of graphene layers. We present an accurate expression for σ1 （ω） in a closed form for a multilayer graphene film supported on a finite-thickness transparent substrate. This form takes into account the coherent and incoherent multiple reflections of the system, whereas the traditional method assumes a semi-infinite substrate. The simulated results for graphene sheets with a layer number N ≤ 10 show that no matter what the transparent substrate is, the accuracy to which σ1 （ω） is determined by applying this expression is improved with no systematic error. Moreover, the layer number N can be exactly determined by simply dividing the σ1 （ω） value of N-layer graphene by the corresponding σ1 （ω） of monolayer graphene, where ωp is the peak frequency of the ordinary dielectric function＇s imaginary part ε1 （ω）of graphene.展开更多
Gate-recessed AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) on sapphire substrates are fabricated.The devices with a gate length of 160nm and a gate periphery of 2 × 75μmexhib...Gate-recessed AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) on sapphire substrates are fabricated.The devices with a gate length of 160nm and a gate periphery of 2 × 75μmexhibit two orders of magnitude reduction in gate leakage current and enhanced off-state breakdown characteristics,compared with conventional HEMTs.Furthermore,the extrinsic transconductance of an MOSHEMT is 237.2mS/mm,only 7% lower than that of Schottky-gate HEMT.An extrinsic current gain cutoff frequency fT of 65 GHz and a maximum oscillation frequency fmax of 123 GHz are deduced from rf small signal measurements.The high fmax demonstrates that gate-recessed MOSHEMTs are of great potential in millimeter wave frequencies.展开更多
基金Supported by the National Natural Science Foundation of China under Grant No 61434006
文摘The InGaAs/InAIAs/InP high electron mobility transistor （HEM：F） structures with lattice-matched and pseudo- morphic channels are grown by gas source molecular beam epitaxy. Effects of Si ^-doping condition and growth interruption on the electrical properties are investigated by changing the Si-cell temperature, doping time and growth process. It is found that the optimal Si ^-doping concentration （Nd） is about 5.0 x 1012 cm-2 and the use of growth interruption has a dramatic effect on the improvement of electrical properties. The material structure and crystal interface are analyzed by secondary ion mass spectroscopy and high resolution transmission elec- tron microscopy. An InGaAs/InAiAs/InP HEMT device with a gate length of lOOnm is fabricated. The device presents good pinch-off characteristics and the kink-effect of the device is trifling. In addition, the device exhibits fT = 249 GHa and fmax 〉 400 GHz.
基金supported by the National Natural Science Foundation of China(Grant Nos.61106060 and 61274059)the National High Technology Research and Development Program of China(Grant No.2012AA052401)
文摘Emitted multi-crystalline silicon and black silicon solar cells are conformal doped by ion implantation using the plasma immersion ion implantation （PⅢ） technique. The non-uniformity of emitter doping is lower than 5 %. The secondary ion mass spectrometer profile indicates that the PⅢ technique obtained 100-rim shallow emitter and the emitter depth could be impelled by furnace annealing to 220 nm and 330 nm at 850 ℃ with one and two hours, respectively. Furnace annealing at 850 ℃ could effectively electrically activate the dopants in the silicon. The efficiency of the black silicon solar cell is 14.84% higher than that of the mc-silicon solar cell due to more incident light being absorbed.
基金Project supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘The positive bias temperature instability（PBTI） degradations of high-k/metal gate（HK/MG） n MOSFETs with thin TiN capping layers（1.4 nm and 2.4 nm） are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI（90℃,125℃, 160℃） are studied and activation energy（Ea） values（0.13 eV and 0.15 eV） are extracted. Although the equivalent oxide thickness（EOT） values of two TiN thickness values are almost similar（0.85 nm and 0.87 nm）, the 2.4-nm TiN one（thicker Ti N capping layer） shows better PBTI reliability（13.41% at 0.9 V, 90℃, 1000 s）. This is due to the better interfacial layer/high-k（IL/HK） interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.
基金Supported by the National Natural Science Foundation of China under Grant No 616340084the Youth Innovation Promotion Association of Chinese Academy of Sciences under Grant No 2014101the Austrian-Chinese Cooperative R&D Projects of International Cooperation Project of Chinese Academy of Sciences under Grant No 172511KYSB20150006
文摘The （60）Co-γ ray total ionizing dose radiation responses of 55-nm silicon-oxide-nitride-oxide-silicon（SONOS） memory cells in pulse mode（programmed/erased with pulse voltage） and dc mode（programmed/erased with direct voltage sweeping） are investigated. The threshold voltage and off-state current of memory cells before and after radiation are measured. The experimental results show that the memory cells in pulse mode have a better radiation-hard capability. The normalized memory window still remains at 60% for cells in dc mode and 76% for cells in pulse mode after 300 krad（Si） radiation. The charge loss process physical mechanisms of programmed SONOS devices during radiation are analyzed.
基金Project supported by the National Natural Science Foundation of China (Grant Nos.12074368,92165207,12034018,and 62004185)the Anhui Province Natural Science Foundation (Grant No.2108085J03)the USTC Tang Scholarship。
文摘The single-shot readout data process is essential for the realization of high-fidelity qubits and fault-tolerant quantum algorithms in semiconductor quantum dots. However, the fidelity and visibility of the readout process are sensitive to the choice of the thresholds and limited by the experimental hardware. By demonstrating the linear dependence between the measured spin state probabilities and readout visibilities along with dark counts, we describe an alternative threshold-independent method for the single-shot readout of spin qubits in semiconductor quantum dots. We can obtain the extrapolated spin state probabilities of the prepared probabilities of the excited spin state through the threshold-independent method. We then analyze the corresponding errors of the method, finding that errors of the extrapolated probabilities cannot be neglected with no constraints on the readout time and threshold voltage. Therefore, by limiting the readout time and threshold voltage, we ensure the accuracy of the extrapolated probability. We then prove that the efficiency and robustness of this method are 60 times larger than those of the most commonly used method. Moreover, we discuss the influence of the electron temperature on the effective area with a fixed external magnetic field and provide a preliminary demonstration for a single-shot readout of up to 0.7K/1.5T in the future.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 12074368, 92165207, 12034018, and 92265113)the Innovation Program for Quantum Science and Technology (Grant No. 2021ZD0302300)+1 种基金the Anhui Province Natural Science Foundation (Grant No. 2108085J03)the USTC Tang Scholarship。
文摘Valley, the intrinsic feature of silicon, is an inescapable subject in silicon-based quantum computing. At the spin–valley hotspot, both Rabi frequency and state relaxation rate are significantly enhanced. With protection against charge noise, the valley degree of freedom is also conceived to encode a qubit to realize noise-resistant quantum computing.Here, based on the spin qubit composed of one or three electrons, we characterize the intrinsic properties of valley in an isotopically enriched silicon quantum dot(QD) device. For one-electron qubit, we measure two electric-dipole spin resonance(EDSR) signals which are attributed to partial occupation of two valley states. The resonance frequencies of two EDSR signals have opposite electric field dependences. Moreover, we characterize the electric field dependence of the upper valley state based on three-electron qubit experiments. The difference of electric field dependences of the two valleys is 52.02 MHz/V, which is beneficial for tuning qubit frequency to meet different experimental requirements. As an extension of electrical control spin qubits, the opposite electric field dependence is crucial for qubit addressability,individual single-qubit control and two-qubit gate approaches in scalable quantum computing.
基金Project supported by the National Basic Research Program of China(Grant No.2010CB327502)
文摘InA1As/InGaAs high electron mobility transistors （HEMTs） on an InP substrate with well-balanced cutoff frequency fT and maximum oscillation frequency frnax are reported. An InA1As/InGaAs HEMT with 100-nm gate length and gate width of 2 × 50 μm shows excellent DC characteristics, including full channel current of 724 mA/mm, extrinsic maximum transconductance gm.max of 1051 mS/mm, and drain-gate breakdown voltage BVDG of 5.92 V. In addition, this device exhibits fT = 249 GHz and fmax = 415 GHz. These results were obtained by fabricating an asymmetrically recessed gate and minimizing the parasitic resistances. The specific Ohmic contact resistance was reduced to 0.031 0.mm. Moreover, the fT obtained in this work is the highest ever reported in 100-nm gate length InA1As/InGaAs InP-based HEMTs. The outstanding gm.max, fT, fmax, and good BVDG make the device suitable for applications in low noise amplifiers, power amplifiers, and high speed circuits.
基金Project supported by the National Science&Technology Major Projects of the Ministry of Science and Technology of China(Grant No.2009ZX02035)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘A new method is proposed to extract the energy distribution of negative charges, which results from electron trapping by traps in the gate stack of n MOSFET during positive bias temperature instability（PBTI） stress based on the recovery measurement. In our case, the extracted energy distribution of negative charges shows an obvious dependence on energy,and the energy level of the largest energy density of negative charges is 0.01 eV above the conduction band of silicon. The charge energy distribution below that energy level shows strong dependence on the stress voltage.
基金Project supported by the Major Program of the National Natural Science Foundation of China （Grant No. 60890191） and the National Key Basic Research Program of China （Grant No. 2010CB327503）.
文摘In this study, the physics-based device simulation tool Silvaco ATLAS is used to characterize the electrical properties of an AlGaN/GaN high electron mobility transistor （HEMT） with a U-type gate foot. The U-gate AlGaN/GaN HEMT mainly features a gradually changed sidewall angle, which effectively mitigates the electric field in the channel, thus obtaining enhanced off-state breakdown characteristics. At the same time, only a small additional gate capacitance and decreased gate resistance ensure excellent RF characteristics for the U-gate device. U-gate AlGaN/GaN HEMTs are feasible through adjusting the etching conditions of an inductively coupled plasma system, without introducing any extra process steps. The simulation results are confirmed by experimental measurements. These features indicate that U-gate A1GaN/GaN HEMTs might be promising candidates for use in millimeter-wave power applications.
文摘During the forming process of the free-standing structure or the functional cavity when releasing the high aspect ratio sacrificial layer, such structures tend to stick to the substrate due to capillary force. This paper describes the application of pull-in length conception as design rules to a novel ＇dimpled＇ method in releasing sacrificial layer. Based on the conception of pull-in length in adhering Phenomenon, the fabrication and releasing sacrificial layer methods using micro bumps based on the silicon substrate were presented. According to the thermal isolation performances of one kind of micro electromechanical system device thermal shear stress sensor, the sacrificial layers were validated to be successfully released.
基金the National Key R&D Program of China(Grant Nos.2018YFB0407501 and 2016YFA0201800)the National Natural Science Foundation of China(Grant Nos.61804173,61922083,61804167,61904200,and 61821091)the fourth China Association for Science and Technology Youth Talent Support Project(Grant No.2019QNRC001).
文摘The resistive random access memory(RRAM)has stimulated a variety of promising applications including programmable analog circuit,massive data storage,neuromorphic computing,etc.These new emerging applications have huge demands on high integration density and low power consumption.The cross-point configuration or passive array,which offers the smallest footprint of cell size and feasible capability of multi-layer stacking,has received broad attention from the research community.In such array,correct operation of reading and writing on a cell relies on effective elimination of the sneaking current coming from the neighboring cells.This target requires nonlinear I-V characteristics of the memory cell,which can be realized by either adding separate selector or developing implicit build-in nonlinear cells.The performance of a passive array largely depends on the cell nonlinearity,reliability,on/off ratio,line resistance,thermal coupling,etc.This article provides a comprehensive review on the progress achieved concerning 3D RRAM integration.First,the authors start with a brief overview of the associative problems in passive array and the category of 3D architectures.Next,the state of the arts on the development of various selector devices and self-selective cells are presented.Key parameters that influence the device nonlinearity and current density are outlined according to the corresponding working principles.Then,the reliability issues in 3D array are summarized in terms of uniformity,endurance,retention,and disturbance.Subsequently,scaling issue and thermal crosstalk in 3D memory array are thoroughly discussed,and applications of 3D RRAM beyond storage,such as neuromorphic computing and CMOL circuit are discussed later.Summary and outlooks are given in the final.
基金the National Natural Science Foundation of China(Grant Nos.61774168 and 11764008)the Opening Project of Key Laboratory of Microelectronic Devices&Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences。
文摘Since defects such as traps and oxygen vacancies exist in dielectrics,it is difficult to fabricate a high-performance MoS_(2)field-effect transistor(FET)using atomic layer deposition(ALD)Al_(2)O_(3)as the gate dielectric layer.In this paper,NH_(3)in situ doping,a process treatment approach during ALD growth of Al_(2)O_(3),is used to decrease these defects for better device characteristics.MoS_(2)FET has been well fabricated with this technique and the effect of different NH_(3)in situ doping sequences in the growth cycle has been investigated in detail.Compared with counterparts,those devices with NH_(3)in situ doping demonstrate obvious performance enhancements:Ion/Ioff is improved by one order of magnitude,from 1.33×10^(5)to 3.56×10^(6),the threshold voltage shifts from-0.74 V to-0.12 V and a small subthreshold swing of 105 m V/dec is achieved.The improved MoS_(2)FET performance is attributed to nitrogen doping by the introduction of NH_(3)during the Al_(2)O_(3)ALD growth process,which leads to a reduction in the surface roughness of the dielectric layer and the repair of oxygen vacancies in the Al_(2)O_(3)layer.Furthermore,the MoS_(2)FET processed by in situ NH_(3)doping after the Al and O precursor filling cycles demonstrates the best performance;this may be because the final NH_(3)doping after film growth restores more oxygen vacancies to screen more charge scattering in the MoS_(2)channel.The reported method provides a promising way to reduce charge scattering in carrier transport for high-performance MoS_(2)devices.
基金supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.
基金Supported by the National Key Research and Development Program of China(2016YFA0301701)the Youth Innovation Promotion Association of CAS under Grant No 2016112
文摘A promising technology named epitaxy on nano-scale freestanding fin （ENFF） is firstly proposed for hetero- epitaxy. This technology can effectively release total strain energy and then can reduce the probability of gener- ating mismatch dislocations. Based on the calculation, dislocation defects can be eliminated completely when the thickness of the Si freestanding fin is less than 10nm for the epitaxial Ge layer. In addition, this proposed ENFF process can provide sufficient uniaxial stress for the epitaxy layer, which can be the major stressor for the SiGe or Ge channel fin field-effect transistor or nanowire at the 10nm node and beyond. According to the results of technology computer-aided design simulation, nanowires integrated with ENFF show excellent electrical perfor- mance for uniaxial stress and band offset. The ENFF process is compatible with the state of the art mainstream technology, which has a good potential for future applications.
文摘Normal-incidence transmission measurements are commonly used for determining the real part of the in-plane optical conductivities σ1 （ω） of graphene layers. We present an accurate expression for σ1 （ω） in a closed form for a multilayer graphene film supported on a finite-thickness transparent substrate. This form takes into account the coherent and incoherent multiple reflections of the system, whereas the traditional method assumes a semi-infinite substrate. The simulated results for graphene sheets with a layer number N ≤ 10 show that no matter what the transparent substrate is, the accuracy to which σ1 （ω） is determined by applying this expression is improved with no systematic error. Moreover, the layer number N can be exactly determined by simply dividing the σ1 （ω） value of N-layer graphene by the corresponding σ1 （ω） of monolayer graphene, where ωp is the peak frequency of the ordinary dielectric function＇s imaginary part ε1 （ω）of graphene.
基金Supported by Major Program of the National Natural Science Foundation of China under Grant No 60890191the National Basic Research Program of China under Grant No 2010CB327503.
文摘Gate-recessed AlGaN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMTs) on sapphire substrates are fabricated.The devices with a gate length of 160nm and a gate periphery of 2 × 75μmexhibit two orders of magnitude reduction in gate leakage current and enhanced off-state breakdown characteristics,compared with conventional HEMTs.Furthermore,the extrinsic transconductance of an MOSHEMT is 237.2mS/mm,only 7% lower than that of Schottky-gate HEMT.An extrinsic current gain cutoff frequency fT of 65 GHz and a maximum oscillation frequency fmax of 123 GHz are deduced from rf small signal measurements.The high fmax demonstrates that gate-recessed MOSHEMTs are of great potential in millimeter wave frequencies.
