TiAIC metal gate for the metal-oxide-semiconductor field-effect-transistor （MOSFET） is grown by the atorr/ic layer deposition method using TiCI4 and AI（CH3） 3 （TMA） as precursors. It is found that the major PrOd...TiAIC metal gate for the metal-oxide-semiconductor field-effect-transistor （MOSFET） is grown by the atorr/ic layer deposition method using TiCI4 and AI（CH3） 3 （TMA） as precursors. It is found that the major PrOduct of the TIC14 and TMA reaction is TiA1C, and the components of C and A1 are found to increase with higher growth temperature. The reaction mechanism is investigated by using x-ray photoemission spectroscopy （XPS）, Fourier transform infrared spectroscopy （FFIR）, and scanning electron microscope （SEM）. The reaction mechanism is as follows. Ti is generated through the reduction of TiCI4 by TMA. The reductive behavior of TMA involves the formation of ethane. The Ti from the reduction of TIC14 by TMA reacts with ethane easily forming heterogenetic TiCH2, TiCH=CH2 and TiC fragments. In addition, TMA thermally decomposes, driving A1 into the TiC film and leading to TiA1C formation. With the growth temperature increasing, TMA decomposes more severely, resulting in more C and A1 in the TiA1C film. Thus, the film composition can be controlled by the growth temperature to a certain extent.展开更多
In this paper, an N-doped titanium oxide （TiO2） photocatalyst is deposited by a plasma-enhanced atomic layer deposition （PEALD） system through the in-situ doping method. X-ray photoelectron spectroscopy （XPS） an...In this paper, an N-doped titanium oxide （TiO2） photocatalyst is deposited by a plasma-enhanced atomic layer deposition （PEALD） system through the in-situ doping method. X-ray photoelectron spectroscopy （XPS） analysis indicates that substitutional nitrogen atoms （-395.9 eV） with 1 atom% are effectively doped into TiO2 films. UV-VIS spectrometry shows that the in-situ nitrogen doping method indeed enhances the visible-activity of TiO2 films in the 425-550 nm range, and the results of the performance tests of the N-doped TiO2 films also imply that the photocatalysis activity is improved by in-situ doping. The in-situ doping mechanism of the N-doped TiO2 film is suggested according to the XPS results and the typical atomic layer deposition process.展开更多
Gd-doped HfO2 has drawn worldwide interest for its interesting features. It is considered to be a suitable material for N-type metal-oxide-semiconductor （MOS） devices due to a negative flatband voltage （Vfb） shift...Gd-doped HfO2 has drawn worldwide interest for its interesting features. It is considered to be a suitable material for N-type metal-oxide-semiconductor （MOS） devices due to a negative flatband voltage （Vfb） shift caused by the Gd doping. In this work, an anomalous positive shift was observed when Gd was doped into HfO2. The cause for such a phenomenon was systematically investigated by distinguishing the effects of different factors, such as Fermi level pinning （FLP）, a dipole at the dielectric/SiO2 interface, fixed interracial charge, and bulk charge, on Vfb. It was found that the FLP and interfacial dipole could make Vfb negatively shifted, which is in agreement with the conventional dipole theory. The increase in interfacial fixed charge resulting from Gd doping plays a major role in positive Vfb shift.展开更多
The kink effect in current-voltage （IV） characteristic s seriously deteriorates the performance of a GaN-based HEMT. Based on a series of direct current （DC） IV measurements in a GaN-based HEMT with an AlGaN back ...The kink effect in current-voltage （IV） characteristic s seriously deteriorates the performance of a GaN-based HEMT. Based on a series of direct current （DC） IV measurements in a GaN-based HEMT with an AlGaN back barrier, a possible mechanism with electron-trapping and detrapping processes is proposed. Kink-related deep levels are activated by a high drain source voltage （Vds） and located in a GaN channel layer. Both electron trapping and detrapping processes are accomplished with the help of hot electrons from the channel by impact ionization. Moreover, the mechanism is verified by two other DC IV measurements and a model with an expression of the kink current.展开更多
Chemical and field-effect passivation of atomic layer deposition （ALD） Al2O3 films are investigated, mainly by corona charging measurement. The interface structure and material properties are characterized by transm...Chemical and field-effect passivation of atomic layer deposition （ALD） Al2O3 films are investigated, mainly by corona charging measurement. The interface structure and material properties are characterized by transmission electron microscopy （TEM） and X-ray photoelectron spectroscopy （XPS）, respectively. Passivation performance is improved remarkably by annealing at temperatures of 450 ℃ and 500 ℃, while the improvement is quite weak at 600 ℃, which can be attributed to the poor quality of chemical passivation. An increase of fixed negative charge density in the films during annealing can be explained by the Al2O3/Si interface structural change. The Al–OH groups play an important role in chemical passivation, and the Al–OH concentration in an as-deposited film subsequently determines the passivation quality of that film when it is annealed, to a certain degree.展开更多
A novel and accurate method is proposed to extract the intrinsic elements of the GaN high-electron-mobility transistor（HEMT） switch.The new extraction method is verified by comparing the simulated S-parameters with ...A novel and accurate method is proposed to extract the intrinsic elements of the GaN high-electron-mobility transistor（HEMT） switch.The new extraction method is verified by comparing the simulated S-parameters with the measured data over the 5-40 GHz frequency range.The percentage errors E（ij） within 3.83% show the great agreement between the simulated S-parameters and the measured data.展开更多
Strained-Si0.73Ge0.27 channels are successfully integrated with high-R/metal gates in p-type metai-oxide- semi- conductor field effect transistors （pMOSFETs） using the replacement post-gate process. A silicon cap an...Strained-Si0.73Ge0.27 channels are successfully integrated with high-R/metal gates in p-type metai-oxide- semi- conductor field effect transistors （pMOSFETs） using the replacement post-gate process. A silicon cap and oxide inter layers are inserted between Si0.73Ge0.27 and high-κ dielectric to improve the interface. The fab- ricated Si0.73Ge0.27 pMOSFETs with gate length of 3Onto exhibit good performance with high drive current （~428μA/μm at VDD = 1 V） and suppressed short-channel effects （DIBL^77mV/V and SS^90mV/decade）. It is found that the enhancement of effective hole mobility is up to 200% in long-gate-length Si0.73Ge0.27-channel pMOSFETs compared with the corresponding silicon transistors. The improvement of device performance is reduced due to strain relaxation as the gate length decreases, while 26% increase of the drive current is still obtained for 30-nm-gate-length Si0.73Ge0.27 devices.展开更多
A new modified Angelov current–voltage characteristic model equation is proposed to improve the drain–source current（Ids） simulation of an Al Ga N/Ga N-based（gallium nitride） high electron mobility transistor（A...A new modified Angelov current–voltage characteristic model equation is proposed to improve the drain–source current（Ids） simulation of an Al Ga N/Ga N-based（gallium nitride） high electron mobility transistor（Al Ga N/Ga N-based HEMT） at high power operation. Since an accurate radio frequency（RF） current simulation is critical for a correct power simulation of the device, in this paper we propose a method of Al Ga N/Ga N high electron mobility transistor（HEMT）nonlinear large-signal model extraction with a supplemental modeling of RF drain–source current as a function of RF input power. The improved results of simulated output power, gain, and power added efficiency（PAE） at class-AB quiescent bias of Vgs =-3.5 V, Vds= 30 V with a frequency of 9.6 GHz are presented.展开更多
The current voltage （IV） characteristics are greatly influenced by the dispersion effects in A1GaN/CaN high electron mobility transistors. The direct current （DC） IV and pulsed IV measurements are performed to giv...The current voltage （IV） characteristics are greatly influenced by the dispersion effects in A1GaN/CaN high electron mobility transistors. The direct current （DC） IV and pulsed IV measurements are performed to give a deep investigation into the dispersion effects, which are mainly related to the trap and self-heating mechanisms. The results show that traps play an important role in the kink effects, and high stress can introduce more traps and defects in the device. With the help of the pulsed IV measurements, the trapping effects and self-heating effects can be separated. The impact of time constants on the dispersion effects is also discussed. In order to achieve an accurate static DC IV measurement, the steady state of the bias points must be considered carefully to avoid the dispersion effects.展开更多
The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,i...The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy（SIMS） analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo（kMC） method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.展开更多
A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/...A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFB of TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results. Furthermore, both positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.展开更多
The growth process of GeOx films formed by plasma post-oxidation （PPO） at room temperature （RT） is investigated using angle-resolved x-ray photoelectron spectroscopy （AR-XPS）. The experimental results show that ...The growth process of GeOx films formed by plasma post-oxidation （PPO） at room temperature （RT） is investigated using angle-resolved x-ray photoelectron spectroscopy （AR-XPS）. The experimental results show that the distributions of the Ge4＋ states, a mixture of the Ge^2＋ and Ge^3＋ states, and the Ge^1＋ states are localized from the GeOx surface to the GeOx/Ge interface. Moreover, the Ge^1＋ states are predominant when the two outermost layers of Ge atoms are oxidized. These findings are helpful for establishing in-depth knowledge of the growth mechanism of the GeOx layer and valuable for the optimization of Ge-based gate stacks for future complementary metal-oxide-semiconductor （MOS） field-effect transistor （CMOSFET） devices.展开更多
The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10...The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.展开更多
Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. ...Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.展开更多
This paper gives a detailed analysis of the time-dependent degradation of the threshold voltage in AlGaN/GaN high electron mobility transistors(HEMTs) submitted to off-state stress. The threshold voltage shows a posit...This paper gives a detailed analysis of the time-dependent degradation of the threshold voltage in AlGaN/GaN high electron mobility transistors(HEMTs) submitted to off-state stress. The threshold voltage shows a positive shift in the early stress, then turns to a negative shift. The negative shift of the threshold voltage seems to have a long recovery time. A model related with the balance of electron trapping and detrapping induced by shallow donors and deep acceptors is proposed to explain this degradation mode.展开更多
We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent pr...We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.展开更多
High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to ...High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.展开更多
A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors （NMOSFETs） is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 ...A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors （NMOSFETs） is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 ？ was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide （TMAH） wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device’s gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μ. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage （～ 0.24 V） for high performance NMOSFETs. The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.展开更多
This paper presents a novel anti-shock bulk silicon etching apparatus for solving a universal problem which occurs when releasing the diaphragm （e.g. SiNx）, that the diaphragm tends to be probably cracked by the imp...This paper presents a novel anti-shock bulk silicon etching apparatus for solving a universal problem which occurs when releasing the diaphragm （e.g. SiNx）, that the diaphragm tends to be probably cracked by the impact of heatinginduced bubbles, the swirling of heating-induced etchant, dithering of the hand and imbalanced etchant pressure during the wafer being taken out. Through finite element methods, the causes of the diaphragm cracking are analysed. The impact of heating-induced bubbles could be the main factor which results in the failure stress of the SiNx diaphragm and the rupture of it. In order to reduce the four potential effects on the cracking of the released diaphragm, an anti-shock hulk silicon etching apparatus is proposed for using during the last etching process of the diaphragm release. That is, the silicon wafer is first put into the regular constant temperature etching apparatus or ultrasonic plus, and when the residual bulk silicon to be etched reaches near the interface of the silicon and SiNx diaphragm, within a distance of 50-80μm （the exact value is determined by the thickness, surface area and intensity of the released diaphragm）, the wafer is taken out carefully and put into the said anti-shock silicon etching apparatus. The wafer＇s position is at the geometrical centre, also the centre of gravity of the etching vessel. An etchant outlet is built at the bottom. The wafer is etched continuously, and at the same time the etchant flows out of the vessel. Optionally, two symmetrically placed low-power heating resistors are put in the anti-shock silicon etching apparatus to quicken the etching process. The heating resistors＇ power should be low enough to avoid the swirling of the heating-induced etchant and the impact of the heating-induced bubbles on the released diaphragm. According to the experimental results, the released SiNx diaphragm thus treated is unbroken, which proves the practicality of the said anti-shock bulk silicon etching apparatus.展开更多
In this paper,the off-state breakdown characteristics of two different AlGaN/GaN high electron mobility transistors（HEMTs）,featuring a 50-nm and a 150-nm GaN thick channel layer,respectively,are compared.The HEMT wi...In this paper,the off-state breakdown characteristics of two different AlGaN/GaN high electron mobility transistors（HEMTs）,featuring a 50-nm and a 150-nm GaN thick channel layer,respectively,are compared.The HEMT with a thick channel exhibits a little larger pinch-off drain current but significantly enhanced off-state breakdown voltage（SVoff）.Device simulation indicates that thickening the channel increases the drain-induced barrier lowering（DIBL） but reduces the lateral electric field in the channel and buffer underneath the gate.The increase of BVoff in the thick channel device is due to the reduction of the electric field.These results demonstrate that it is necessary to select an appropriate channel thickness to balance DIBL and BVoff in AlGaN/GaN HEMTs.展开更多
基金Project supported by the Key Technology Study for 16/14 nm Program of the Ministry of Science and Technology of China(Grant No.2013ZX02303)
文摘TiAIC metal gate for the metal-oxide-semiconductor field-effect-transistor （MOSFET） is grown by the atorr/ic layer deposition method using TiCI4 and AI（CH3） 3 （TMA） as precursors. It is found that the major PrOduct of the TIC14 and TMA reaction is TiA1C, and the components of C and A1 are found to increase with higher growth temperature. The reaction mechanism is investigated by using x-ray photoemission spectroscopy （XPS）, Fourier transform infrared spectroscopy （FFIR）, and scanning electron microscope （SEM）. The reaction mechanism is as follows. Ti is generated through the reduction of TiCI4 by TMA. The reductive behavior of TMA involves the formation of ethane. The Ti from the reduction of TIC14 by TMA reacts with ethane easily forming heterogenetic TiCH2, TiCH=CH2 and TiC fragments. In addition, TMA thermally decomposes, driving A1 into the TiC film and leading to TiA1C formation. With the growth temperature increasing, TMA decomposes more severely, resulting in more C and A1 in the TiA1C film. Thus, the film composition can be controlled by the growth temperature to a certain extent.
基金supported by the National Science and Technology Major Project of China(No.2009ZX02037-003)China Postdoctoral Science Foundation(No.2011M500996)the Opening Project of Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences
文摘In this paper, an N-doped titanium oxide （TiO2） photocatalyst is deposited by a plasma-enhanced atomic layer deposition （PEALD） system through the in-situ doping method. X-ray photoelectron spectroscopy （XPS） analysis indicates that substitutional nitrogen atoms （-395.9 eV） with 1 atom% are effectively doped into TiO2 films. UV-VIS spectrometry shows that the in-situ nitrogen doping method indeed enhances the visible-activity of TiO2 films in the 425-550 nm range, and the results of the performance tests of the N-doped TiO2 films also imply that the photocatalysis activity is improved by in-situ doping. The in-situ doping mechanism of the N-doped TiO2 film is suggested according to the XPS results and the typical atomic layer deposition process.
基金Project supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(Grant No.2009ZX02035)the National Natural Science of China(Grant Nos.61176091 and 50932001)
文摘Gd-doped HfO2 has drawn worldwide interest for its interesting features. It is considered to be a suitable material for N-type metal-oxide-semiconductor （MOS） devices due to a negative flatband voltage （Vfb） shift caused by the Gd doping. In this work, an anomalous positive shift was observed when Gd was doped into HfO2. The cause for such a phenomenon was systematically investigated by distinguishing the effects of different factors, such as Fermi level pinning （FLP）, a dipole at the dielectric/SiO2 interface, fixed interracial charge, and bulk charge, on Vfb. It was found that the FLP and interfacial dipole could make Vfb negatively shifted, which is in agreement with the conventional dipole theory. The increase in interfacial fixed charge resulting from Gd doping plays a major role in positive Vfb shift.
基金Project supported by the Program for New Century Excellent Talents in University,China (Grant No.NCET-12-0915)
文摘The kink effect in current-voltage （IV） characteristic s seriously deteriorates the performance of a GaN-based HEMT. Based on a series of direct current （DC） IV measurements in a GaN-based HEMT with an AlGaN back barrier, a possible mechanism with electron-trapping and detrapping processes is proposed. Kink-related deep levels are activated by a high drain source voltage （Vds） and located in a GaN channel layer. Both electron trapping and detrapping processes are accomplished with the help of hot electrons from the channel by impact ionization. Moreover, the mechanism is verified by two other DC IV measurements and a model with an expression of the kink current.
基金Project supported by the National Natural Science Foundation of China(Grant No.61106060)the Knowledge Innovation Program of the Chinese Academy of Sciences(Grant No.Y2YF028001)the National High Technology Research and Development Program of China(Grant No.2012AA052401)
文摘Chemical and field-effect passivation of atomic layer deposition （ALD） Al2O3 films are investigated, mainly by corona charging measurement. The interface structure and material properties are characterized by transmission electron microscopy （TEM） and X-ray photoelectron spectroscopy （XPS）, respectively. Passivation performance is improved remarkably by annealing at temperatures of 450 ℃ and 500 ℃, while the improvement is quite weak at 600 ℃, which can be attributed to the poor quality of chemical passivation. An increase of fixed negative charge density in the films during annealing can be explained by the Al2O3/Si interface structural change. The Al–OH groups play an important role in chemical passivation, and the Al–OH concentration in an as-deposited film subsequently determines the passivation quality of that film when it is annealed, to a certain degree.
文摘A novel and accurate method is proposed to extract the intrinsic elements of the GaN high-electron-mobility transistor（HEMT） switch.The new extraction method is verified by comparing the simulated S-parameters with the measured data over the 5-40 GHz frequency range.The percentage errors E（ij） within 3.83% show the great agreement between the simulated S-parameters and the measured data.
基金Supported by the National Basic Research Program of China under Grant No 2011CBA00605the National Natural Science Foundation of China under Grant No 61404165
文摘Strained-Si0.73Ge0.27 channels are successfully integrated with high-R/metal gates in p-type metai-oxide- semi- conductor field effect transistors （pMOSFETs） using the replacement post-gate process. A silicon cap and oxide inter layers are inserted between Si0.73Ge0.27 and high-κ dielectric to improve the interface. The fab- ricated Si0.73Ge0.27 pMOSFETs with gate length of 3Onto exhibit good performance with high drive current （~428μA/μm at VDD = 1 V） and suppressed short-channel effects （DIBL^77mV/V and SS^90mV/decade）. It is found that the enhancement of effective hole mobility is up to 200% in long-gate-length Si0.73Ge0.27-channel pMOSFETs compared with the corresponding silicon transistors. The improvement of device performance is reduced due to strain relaxation as the gate length decreases, while 26% increase of the drive current is still obtained for 30-nm-gate-length Si0.73Ge0.27 devices.
基金Project supported by the National Natural Science Foundation of China(Grant No.61204086)
文摘A new modified Angelov current–voltage characteristic model equation is proposed to improve the drain–source current（Ids） simulation of an Al Ga N/Ga N-based（gallium nitride） high electron mobility transistor（Al Ga N/Ga N-based HEMT） at high power operation. Since an accurate radio frequency（RF） current simulation is critical for a correct power simulation of the device, in this paper we propose a method of Al Ga N/Ga N high electron mobility transistor（HEMT）nonlinear large-signal model extraction with a supplemental modeling of RF drain–source current as a function of RF input power. The improved results of simulated output power, gain, and power added efficiency（PAE） at class-AB quiescent bias of Vgs =-3.5 V, Vds= 30 V with a frequency of 9.6 GHz are presented.
基金Project supported by the National Basic Research Program of China (Grant No.2010CB327503)the National Natural Science Foundation of China (Grant No.60890191)
文摘The current voltage （IV） characteristics are greatly influenced by the dispersion effects in A1GaN/CaN high electron mobility transistors. The direct current （DC） IV and pulsed IV measurements are performed to give a deep investigation into the dispersion effects, which are mainly related to the trap and self-heating mechanisms. The results show that traps play an important role in the kink effects, and high stress can introduce more traps and defects in the device. With the help of the pulsed IV measurements, the trapping effects and self-heating effects can be separated. The impact of time constants on the dispersion effects is also discussed. In order to achieve an accurate static DC IV measurement, the steady state of the bias points must be considered carefully to avoid the dispersion effects.
基金supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)the Opening Project of Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Micro Electronics of Chinese Academy of Sciences
文摘The thickness effect of the TiN capping layer on the time dependent dielectric breakdown（TDDB） characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper.Based on experimental results,it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer.From the charge pumping measurement and secondary ion mass spectroscopy（SIMS） analysis,it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density.In addition,the influences of interface and bulk trap density ratio Nit/Not are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo（kMC） method.The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses.
基金supported by the National Natural Science of China(Grant Nos.61176091 and 50932001)
文摘A theoretical model of flatband voltage （VFB） of metal/high-k/Si02/Si stack is proposed based on band alignment of entire gate stack, i.e., the VFB is obtained by simultaneously considering band alignments of metal/high-k, high-k/SiO2 and SiO2/Si interfaces, and their interactions. Then the VFB of TiN/HfO2/SiO2/Si stack is experimentally obtained and theoretically investigated by this model. The theoretical calculations are in good agreement with the experimental results. Furthermore, both positive VFB shift of TiN/HfO2/SiO2/Si stack and Fermi level pinning are successfully interpreted and attributed to the dielectric contact induced gap states at TiN/HfO2 and HfO2/SiO2 interfaces.
基金supported by the National Natural Science Foundation of China(Grant Nos.61574168 and 61504163)
文摘The growth process of GeOx films formed by plasma post-oxidation （PPO） at room temperature （RT） is investigated using angle-resolved x-ray photoelectron spectroscopy （AR-XPS）. The experimental results show that the distributions of the Ge4＋ states, a mixture of the Ge^2＋ and Ge^3＋ states, and the Ge^1＋ states are localized from the GeOx surface to the GeOx/Ge interface. Moreover, the Ge^1＋ states are predominant when the two outermost layers of Ge atoms are oxidized. These findings are helpful for establishing in-depth knowledge of the growth mechanism of the GeOx layer and valuable for the optimization of Ge-based gate stacks for future complementary metal-oxide-semiconductor （MOS） field-effect transistor （CMOSFET） devices.
基金Supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China under Grant No 2013ZX02305
文摘The fabrication and characterization of 1700 V 7 A 4H-SiC vertical double-implanted metal-oxide-semiconductor field-effect transistors （VDMOSFETs） are reported. The drift layer is 17μm in thickness with 5 × 10^15 cm^-3 n-type doping, and the channel length is 1μm. The MOSFETs show a peak mobility of 17cm2/V.s and a typical threshold voltage of 3 V. The active area of 0.028cm2 delivers a forward drain current of 7A at Vcs = 22 V and VDS= 15 V. The specific on-resistance （Ron,sv） is 18mΩ.cm2 at VGS= 22 V and the blocking voltage is 1975 V （IDS 〈 lOOnA） at VGS = 0 V.
基金Supported by the National Science and Technology Major Project of China under Grant No 2011ZX02708-003the National Natural Science Foundation of China under Grant No 61504165the Opening Project of Key Laboratory of Microelectronics Devices and Integrated Technology of Institute of Microelectronics of Chinese Academy of Sciences
文摘Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.
基金Project supported by the Program for New Century Excellent Talents in Universities, China （Grant No. NCET-12-0915）.
文摘This paper gives a detailed analysis of the time-dependent degradation of the threshold voltage in AlGaN/GaN high electron mobility transistors(HEMTs) submitted to off-state stress. The threshold voltage shows a positive shift in the early stress, then turns to a negative shift. The negative shift of the threshold voltage seems to have a long recovery time. A model related with the balance of electron trapping and detrapping induced by shallow donors and deep acceptors is proposed to explain this degradation mode.
基金Supported by the National Science and Technology Major Project of China under Grant No 2013ZX02303007the National Key Research and Development Program of China under Grant No 2016YFA0301701the Youth Innovation Promotion Association of the Chinese Academy of Sciences under Grant No 2016112
文摘We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.
基金supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)the Opening Project of Key Laboratory of Microelectronics Devices&Integrated Technology,Institute of Micro Electronics of Chinese Academy of Sciences
文摘High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes.The reliability of thin dielectric films becomes a limitation to device manufacturing,especially to the breakdown characteristic.In this work,a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up,and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation.It is found that all degradation factors,such as trap generation rate time exponent m,Weibull slope β and percolation factor s,each could be expressed as a function of trap density time exponent α.Based on the percolation relation and power law lifetime projection,a temperature related trap generation model is proposed.The validity of this model is confirmed by comparing with experiment results.For other device and material conditions,the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.
基金Project supported by the Beijing Natural Science Foundation,China(Grant No.4123106)the National Science and Technology Major Projects of the Ministry of Science and Technology of China(Grant No.2009ZX02035)
文摘A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors （NMOSFETs） is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 ？ was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide （TMAH） wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device’s gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μ. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage （～ 0.24 V） for high performance NMOSFETs. The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.
文摘This paper presents a novel anti-shock bulk silicon etching apparatus for solving a universal problem which occurs when releasing the diaphragm （e.g. SiNx）, that the diaphragm tends to be probably cracked by the impact of heatinginduced bubbles, the swirling of heating-induced etchant, dithering of the hand and imbalanced etchant pressure during the wafer being taken out. Through finite element methods, the causes of the diaphragm cracking are analysed. The impact of heating-induced bubbles could be the main factor which results in the failure stress of the SiNx diaphragm and the rupture of it. In order to reduce the four potential effects on the cracking of the released diaphragm, an anti-shock hulk silicon etching apparatus is proposed for using during the last etching process of the diaphragm release. That is, the silicon wafer is first put into the regular constant temperature etching apparatus or ultrasonic plus, and when the residual bulk silicon to be etched reaches near the interface of the silicon and SiNx diaphragm, within a distance of 50-80μm （the exact value is determined by the thickness, surface area and intensity of the released diaphragm）, the wafer is taken out carefully and put into the said anti-shock silicon etching apparatus. The wafer＇s position is at the geometrical centre, also the centre of gravity of the etching vessel. An etchant outlet is built at the bottom. The wafer is etched continuously, and at the same time the etchant flows out of the vessel. Optionally, two symmetrically placed low-power heating resistors are put in the anti-shock silicon etching apparatus to quicken the etching process. The heating resistors＇ power should be low enough to avoid the swirling of the heating-induced etchant and the impact of the heating-induced bubbles on the released diaphragm. According to the experimental results, the released SiNx diaphragm thus treated is unbroken, which proves the practicality of the said anti-shock bulk silicon etching apparatus.
基金supported by the Program for New Century Excellent Talents in University(Grant No.NCET-12-0915)the National Natural Science Foundation of China(Grant Nos.61334002 and 61204086)
文摘In this paper,the off-state breakdown characteristics of two different AlGaN/GaN high electron mobility transistors（HEMTs）,featuring a 50-nm and a 150-nm GaN thick channel layer,respectively,are compared.The HEMT with a thick channel exhibits a little larger pinch-off drain current but significantly enhanced off-state breakdown voltage（SVoff）.Device simulation indicates that thickening the channel increases the drain-induced barrier lowering（DIBL） but reduces the lateral electric field in the channel and buffer underneath the gate.The increase of BVoff in the thick channel device is due to the reduction of the electric field.These results demonstrate that it is necessary to select an appropriate channel thickness to balance DIBL and BVoff in AlGaN/GaN HEMTs.
