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Infrared image segmentation method based on 2D histogram shape modification and optimal objective function 被引量:8
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作者 Songtao Liu Donghua Gao Fuliang Yin 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 2013年第3期528-536,共9页
In the methods of image thresholding segmentation, such methods based on two-dimensional (2D) histogram and optimal objective functions are important. However, when they are used for infrared image segmentation, the... In the methods of image thresholding segmentation, such methods based on two-dimensional (2D) histogram and optimal objective functions are important. However, when they are used for infrared image segmentation, they are weak in suppressing background noises and worse in segmenting targets with non-uniform gray level. The concept of 2D histogram shape modification is proposed, which is realized by target information prior restraint after enhancing target information using plateau histogram equalization. The formula of 2D minimum Renyi entropy is deduced for image segmentation, then the shape-modified 2D histogram is combined wfth four optimal objective functions (i.e., maximum between-class variance, maximum entropy, maximum correlation and minimum Renyi entropy) respectively for the appli- cation of infrared image segmentation. Simultaneously, F-measure is introduced to evaluate the segmentation effects objectively. The experimental results show that F-measure is an effective evaluation index for image segmentation since its value is fully consistent with the subjective evaluation, and after 2D histogram shape modification, the methods of optimal objective functions can overcome their original forms' deficiency and their segmentation effects are more or less improvements, where the best one is the maximum entropy method based on 2D histogram shape modification. 展开更多
关键词 infrared image segmentation 2D histogram Otsu maximum entropy maximum correlation minimum Renyi entropy.
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Virtual reconfigurable architecture for evolving combinational logic circuits 被引量:4
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作者 王进 LEE Chong-Ho 《Journal of Central South University》 SCIE EI CAS 2014年第5期1862-1870,共9页
A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral com... A virtual reconfigurable architecture(VRA)-based evolvable hardware is proposed for automatic synthesis of combinational logic circuits at gate-level.The proposed VRA is implemented by a Celoxica RC1000 peripheral component interconnect(PCI)board with an Xilinx Virtex xcv2000E field programmable gate array(FPGA).To improve the quality of the evolved circuits,the VRA works through a two-stage evolution: finding a functional circuit and minimizing the number of logic gates used in a feasible circuit.To optimize the algorithm performance in the two-stage evolutionary process and set free the user from the time-consuming process of mutation parameter tuning,a self-adaptive mutation rate control(SAMRC)scheme is introduced.In the evolutionary process,the mutation rate control parameters are encoded as additional genes in the chromosome and also undergo evolutionary operations.The efficiency of the proposed methodology is tested with the evolutions of a 4-bit even parity function,a 2-bit multiplier,and a 3-bit multiplier.The obtained results demonstrate that our scheme improves the evolutionary design of combinational logic circuits in terms of quality of the evolved circuit as well as the computational effort,when compared to the existing evolvable hardware approaches. 展开更多
关键词 evolutionary algorithm evolvable hardware self-adaptive mutation rate control virtual reconfigurable architecture
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