The study projects a flexible and compact wearable pear-shaped Super High Frequency(SHF)antenna that can provide detailed location recognition and tracking applicable to defense beacon technology.This mini aperture wi...The study projects a flexible and compact wearable pear-shaped Super High Frequency(SHF)antenna that can provide detailed location recognition and tracking applicable to defense beacon technology.This mini aperture with electrical dimensions of 0.12λ_(0)×0.22λ_(0)×0.01λ_(0)attains a vast bandwidth over 3.1-34.5 GHz Super High Frequency(SHF)frequency band at S_(11)≤-10 dB,peak gain of 7.14 dBi and proportionately homogeneous radiation pattern.The fractional bandwidth(%BW)acquired is 168%that envelopes diversified frequency spectrum inclusive of X band specifically targeted to all kinds of defense and military operations.The proposed antenna can be worn on a soldier's uniform and hence the Specific Absorption Rate simulation is accomplished.The Peak SAR Value over 1 g of tissue is 1.48 W/kg and for 10 g of tissue is 0.27 W/kg well under the safety standards.The flexibility is proven by analyzing the full electromagnetic simulations for various bending conditions.Time response analysis is attained with its Fidelity Factor and Group Delay.Communication excellence is determined using Link Budget Analysis and it is seen that margin at 100 Mbps is 62 m and at 200 Mbps is 59 m.Prototype is fabricated along with experimental validation.All the results show harmony in shaping the antenna to provide critical situational awareness and data sharing capabilities required in defense beacon technology for location identification.展开更多
High resolution cameras and multi camera systems are being used in areas of video surveillance like security of public places, traffic monitoring, and military and satellite imaging. This leads to a demand for computa...High resolution cameras and multi camera systems are being used in areas of video surveillance like security of public places, traffic monitoring, and military and satellite imaging. This leads to a demand for computational algorithms for real time processing of high resolution videos. Motion detection and background separation play a vital role in capturing the object of interest in surveillance videos, but as we move towards high resolution cameras, the time-complexity of the algorithm increases and thus fails to be a part of real time systems. Parallel architecture provides a surpass platform to work efficiently with complex algorithmic solutions. In this work, a method was proposed for identifying the moving objects perfectly in the videos using adaptive background making, motion detection and object estimation. The pre-processing part includes an adaptive block background making model and a dynamically adaptive thresholding technique to estimate the moving objects. The post processing includes a competent parallel connected component labelling algorithm to estimate perfectly the objects of interest. New parallel processing strategies are developed on each stage of the algorithm to reduce the time-complexity of the system. This algorithm has achieved a average speedup of 12.26 times for lower resolution video frames(320×240, 720×480, 1024×768) and 7.30 times for higher resolution video frames(1360×768, 1920×1080, 2560×1440) on GPU, which is superior to CPU processing. Also, this algorithm was tested by changing the number of threads in a thread block and the minimum execution time has been achieved for 16×16 thread block. And this algorithm was tested on a night sequence where the amount of light in the scene is very less and still the algorithm has given a significant speedup and accuracy in determining the object.展开更多
On augmentation of past work, an effective Wiener filter and its application for noise suppression combined with a formed CORDIC based FFT/IFFT processor with improved speed were executed. The pipelined methodology wa...On augmentation of past work, an effective Wiener filter and its application for noise suppression combined with a formed CORDIC based FFT/IFFT processor with improved speed were executed. The pipelined methodology was embraced for expanding the execution of the system. The proposed Wiener filter was planned in such an approach to evacuate the iteration issues in ordinary Wiener filter. The division process was supplanted by a productive inverse and multiplication process in the proposed design. An enhanced design for matrix inverse with reduced computation complexity was executed. The wide-ranging framework processing was focused around IEEE-754 standard single precision floating point numbers. The Wiener filter and the entire system design was integrated and actualized on VIRTEX 5 FPGA stage and re-enacted to approve the results in Xilinx ISE 13.4. The results show that a productive decrease in power and area is developed by adjusting the proposed technique for speech signal noise degradation with latency of n/2 clock cycles and substantial throughput result per every 12 clock cycles for n-bit precision. The execution of proposed design is exposed to be 31.35% more effective than that of prevailing strategies.展开更多
Support vector machine(SVM)has a good application prospect for speech recognition problems;still optimum parameter selection is a vital issue for it.To improve the learning ability of SVM,a method for searching the op...Support vector machine(SVM)has a good application prospect for speech recognition problems;still optimum parameter selection is a vital issue for it.To improve the learning ability of SVM,a method for searching the optimal parameters based on integration of predator prey optimization(PPO)and Hooke-Jeeves method has been proposed.In PPO technique,population consists of prey and predator particles.The prey particles search the optimum solution and predator always attacks the global best prey particle.The solution obtained by PPO is further improved by applying Hooke-Jeeves method.Proposed method is applied to recognize isolated words in a Hindi speech database and also to recognize words in a benchmark database TI-20 in clean and noisy environment.A recognition rate of 81.5%for Hindi database and 92.2%for TI-20 database has been achieved using proposed technique.展开更多
In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product uni...In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.展开更多
基金the Defense Institute of Advanced Technology,Pune(DIAT,Pune)IIT Delhi。
文摘The study projects a flexible and compact wearable pear-shaped Super High Frequency(SHF)antenna that can provide detailed location recognition and tracking applicable to defense beacon technology.This mini aperture with electrical dimensions of 0.12λ_(0)×0.22λ_(0)×0.01λ_(0)attains a vast bandwidth over 3.1-34.5 GHz Super High Frequency(SHF)frequency band at S_(11)≤-10 dB,peak gain of 7.14 dBi and proportionately homogeneous radiation pattern.The fractional bandwidth(%BW)acquired is 168%that envelopes diversified frequency spectrum inclusive of X band specifically targeted to all kinds of defense and military operations.The proposed antenna can be worn on a soldier's uniform and hence the Specific Absorption Rate simulation is accomplished.The Peak SAR Value over 1 g of tissue is 1.48 W/kg and for 10 g of tissue is 0.27 W/kg well under the safety standards.The flexibility is proven by analyzing the full electromagnetic simulations for various bending conditions.Time response analysis is attained with its Fidelity Factor and Group Delay.Communication excellence is determined using Link Budget Analysis and it is seen that margin at 100 Mbps is 62 m and at 200 Mbps is 59 m.Prototype is fabricated along with experimental validation.All the results show harmony in shaping the antenna to provide critical situational awareness and data sharing capabilities required in defense beacon technology for location identification.
文摘High resolution cameras and multi camera systems are being used in areas of video surveillance like security of public places, traffic monitoring, and military and satellite imaging. This leads to a demand for computational algorithms for real time processing of high resolution videos. Motion detection and background separation play a vital role in capturing the object of interest in surveillance videos, but as we move towards high resolution cameras, the time-complexity of the algorithm increases and thus fails to be a part of real time systems. Parallel architecture provides a surpass platform to work efficiently with complex algorithmic solutions. In this work, a method was proposed for identifying the moving objects perfectly in the videos using adaptive background making, motion detection and object estimation. The pre-processing part includes an adaptive block background making model and a dynamically adaptive thresholding technique to estimate the moving objects. The post processing includes a competent parallel connected component labelling algorithm to estimate perfectly the objects of interest. New parallel processing strategies are developed on each stage of the algorithm to reduce the time-complexity of the system. This algorithm has achieved a average speedup of 12.26 times for lower resolution video frames(320×240, 720×480, 1024×768) and 7.30 times for higher resolution video frames(1360×768, 1920×1080, 2560×1440) on GPU, which is superior to CPU processing. Also, this algorithm was tested by changing the number of threads in a thread block and the minimum execution time has been achieved for 16×16 thread block. And this algorithm was tested on a night sequence where the amount of light in the scene is very less and still the algorithm has given a significant speedup and accuracy in determining the object.
文摘On augmentation of past work, an effective Wiener filter and its application for noise suppression combined with a formed CORDIC based FFT/IFFT processor with improved speed were executed. The pipelined methodology was embraced for expanding the execution of the system. The proposed Wiener filter was planned in such an approach to evacuate the iteration issues in ordinary Wiener filter. The division process was supplanted by a productive inverse and multiplication process in the proposed design. An enhanced design for matrix inverse with reduced computation complexity was executed. The wide-ranging framework processing was focused around IEEE-754 standard single precision floating point numbers. The Wiener filter and the entire system design was integrated and actualized on VIRTEX 5 FPGA stage and re-enacted to approve the results in Xilinx ISE 13.4. The results show that a productive decrease in power and area is developed by adjusting the proposed technique for speech signal noise degradation with latency of n/2 clock cycles and substantial throughput result per every 12 clock cycles for n-bit precision. The execution of proposed design is exposed to be 31.35% more effective than that of prevailing strategies.
文摘Support vector machine(SVM)has a good application prospect for speech recognition problems;still optimum parameter selection is a vital issue for it.To improve the learning ability of SVM,a method for searching the optimal parameters based on integration of predator prey optimization(PPO)and Hooke-Jeeves method has been proposed.In PPO technique,population consists of prey and predator particles.The prey particles search the optimum solution and predator always attacks the global best prey particle.The solution obtained by PPO is further improved by applying Hooke-Jeeves method.Proposed method is applied to recognize isolated words in a Hindi speech database and also to recognize words in a benchmark database TI-20 in clean and noisy environment.A recognition rate of 81.5%for Hindi database and 92.2%for TI-20 database has been achieved using proposed technique.
文摘In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.
