The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is present...The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is presented. It has many promising characteristics such as powerful computing capability, broad I/O bandwidth, topology flexibility, and expansibility. The parallel system performance is evaluated by practical experiment.展开更多
ADSP-TS101 is a high performance DSP with good properties of parallel processing and high speed.According to the real-time processing requirements of underwater acoustic communication algorithms,a real-time parallel p...ADSP-TS101 is a high performance DSP with good properties of parallel processing and high speed.According to the real-time processing requirements of underwater acoustic communication algorithms,a real-time parallel processing system with multi-channel synchronous sample,which is composed of multiple ADSP-TS101s,is designed and carried out.For the hardware design,field programmable gate array(FPGA)logical control is adopted for the design of multi-channel synchronous sample module and cluster/data flow associated pin connection mode is adopted for multiprocessing parallel processing configuration respectively.And the software is optimized by two kinds of communication ways:broadcast writing way through shared bus and point-to-point way through link ports.Through the whole system installation,connective debugging,and experiments in a lake,the results show that the real-time parallel processing system has good stability and real-time processing capability and meets the technical design requirements of real-time processing.展开更多
A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly...A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.展开更多
A novel reconfigurable hardware system which uses both muhi-DSP and FPGA to attain high performance and real-time image processing are presented. The system structure and working principle of mainly processing multi-B...A novel reconfigurable hardware system which uses both muhi-DSP and FPGA to attain high performance and real-time image processing are presented. The system structure and working principle of mainly processing multi-BSP board, extended multi-DSP board are analysed. The outstanding advantage is that the communication among different board components of this system is supported by high speed link ports ＆ serial ports for increasing the system performance and computational power. Then the implementation of embedded real-time operating systems （RTOS） by us is discussed in detail. In this system, we adopt two kinds of parallel structures controlled by RTOS for parallel processing of algorithms. The experimental results show that exploitive period of the system is short, and maintenance convenient. Thus it is suitable for real-time image processing and can get satisfactory effect of image recognition.展开更多
为解决语音增强任务中语音信息未充分利用的问题,提出一种基于深度学习的方法,即融合精确比值掩蔽的门控扩张循环卷积神经网络(gate-dilated recurrent convolutional neural network with accurate ratio masking, GDRCNN-ARM)。GDRCN...为解决语音增强任务中语音信息未充分利用的问题,提出一种基于深度学习的方法,即融合精确比值掩蔽的门控扩张循环卷积神经网络(gate-dilated recurrent convolutional neural network with accurate ratio masking, GDRCNN-ARM)。GDRCNN由编码器、循环卷积层和解码器3部分组成,编码器中借助扩张卷积和门控机制实现对上下文语音信息的捕获,进行并行处理;循环卷积层采用GRU且引入多头注意力机制,捕捉网络中的长期依赖关系;解码器采用逐层解码且通过跳跃连接进行编码器信息的复用,实现对语音细节的还原。实验数据表明,GDRCNN网络在参数量和模型大小方面明显优于DNN、CRN等网络,PESQ平均提高了0.612、0.158,STOI平均提高了0.072、0.020,在语音增强和泛化方面表现出色。展开更多
基金This project was supported by the National Natural Science Foundation of China (60135020).
文摘The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is presented. It has many promising characteristics such as powerful computing capability, broad I/O bandwidth, topology flexibility, and expansibility. The parallel system performance is evaluated by practical experiment.
基金Sponsored by National Natural Science Foundation of China(60572098)
文摘ADSP-TS101 is a high performance DSP with good properties of parallel processing and high speed.According to the real-time processing requirements of underwater acoustic communication algorithms,a real-time parallel processing system with multi-channel synchronous sample,which is composed of multiple ADSP-TS101s,is designed and carried out.For the hardware design,field programmable gate array(FPGA)logical control is adopted for the design of multi-channel synchronous sample module and cluster/data flow associated pin connection mode is adopted for multiprocessing parallel processing configuration respectively.And the software is optimized by two kinds of communication ways:broadcast writing way through shared bus and point-to-point way through link ports.Through the whole system installation,connective debugging,and experiments in a lake,the results show that the real-time parallel processing system has good stability and real-time processing capability and meets the technical design requirements of real-time processing.
文摘A systolic array architecture computer (FXCQ) has been designed for signal processing. R can handle floating point data at very high speed. It is composed of 16 processing cells and a cache that are connected linearly and form a ring structure. All processing cells are identical and programmable. Each processing cell has the peak performance of 20 million floating-point operations per second (20MFLOPS). The machine therefore has a peak performance of 320 M FLOPS. It is integrated as an attached processor into a host system through VME bus interface. Programs for FXCQ are written in a high-level language -B language, which is supported by a parallel optimizing compiler. This paper describes the architecture of FXCQ, B language and its compiler.
基金This project was supported by the National Natural Science Foundation of China(60135020) National Key Pre-researchProject of China(413010701 -3) .
文摘A novel reconfigurable hardware system which uses both muhi-DSP and FPGA to attain high performance and real-time image processing are presented. The system structure and working principle of mainly processing multi-BSP board, extended multi-DSP board are analysed. The outstanding advantage is that the communication among different board components of this system is supported by high speed link ports ＆ serial ports for increasing the system performance and computational power. Then the implementation of embedded real-time operating systems （RTOS） by us is discussed in detail. In this system, we adopt two kinds of parallel structures controlled by RTOS for parallel processing of algorithms. The experimental results show that exploitive period of the system is short, and maintenance convenient. Thus it is suitable for real-time image processing and can get satisfactory effect of image recognition.
文摘为解决语音增强任务中语音信息未充分利用的问题,提出一种基于深度学习的方法,即融合精确比值掩蔽的门控扩张循环卷积神经网络(gate-dilated recurrent convolutional neural network with accurate ratio masking, GDRCNN-ARM)。GDRCNN由编码器、循环卷积层和解码器3部分组成,编码器中借助扩张卷积和门控机制实现对上下文语音信息的捕获,进行并行处理;循环卷积层采用GRU且引入多头注意力机制,捕捉网络中的长期依赖关系;解码器采用逐层解码且通过跳跃连接进行编码器信息的复用,实现对语音细节的还原。实验数据表明,GDRCNN网络在参数量和模型大小方面明显优于DNN、CRN等网络,PESQ平均提高了0.612、0.158,STOI平均提高了0.072、0.020,在语音增强和泛化方面表现出色。
