A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. ...A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.展开更多
SiC MOS器件氧化膜可靠性是SiC器件研究中的重要方面。本文对4H-SiC MOS结构进行电子回旋共振(ECR)氮等离子体氧化后退火工艺处理,采用阶跃电流经时击穿以及XPS分析的方法对其氧化膜稳定性进行了电学以及物理性质方面上的分析。经分析...SiC MOS器件氧化膜可靠性是SiC器件研究中的重要方面。本文对4H-SiC MOS结构进行电子回旋共振(ECR)氮等离子体氧化后退火工艺处理,采用阶跃电流经时击穿以及XPS分析的方法对其氧化膜稳定性进行了电学以及物理性质方面上的分析。经分析氮等离子体处理8min的样品击穿时间和单位面积击穿电荷量都有了明显提高,并且早期失效比率有了明显降低。实验结果表明,经过适当时间的处理,ECR氮等离子体氧化后退火工艺可以有效地降低界面缺陷的密度,提高界面处激活能,从而提高绝缘膜耐受电流应力的能力。展开更多
基金supported by the National High Technology Research and Development Program of China(Grant No.SS2015AA010601)the National Natural Science Foundation of China(Grant Nos.61176091 and 61306129)
文摘A multi-deposition multi-annealing technique （MDMA） is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device＇s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown （TDDB） characteristics of positive channel metal oxide semiconductor （PMOS） under different MDMA process conditions, including the depo- sition/annealing （D＆A） cycles, the D＆A time, and the total annealing time. The results show that the increases of the number of D＆A cycles （from 1 to 2） and D＆A time （from 15 s to 30 s） can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail （TTF） at 63.2% increases by about several times. However, too many D＆A cycles （such as 4 cycles） make the equivalent oxide thickness （EOT） increase by about 1A and the TTF of PMOS worsen. Moreover, different D＆A times and numbers of D＆A cycles induce different breakdown mechanisms.
基金The Special funds for Major State Basic Research Projects under Grant G2000036504,andin part by National High Technology Research and Development Program of China under Grant2003AA1Z1370
