To analyze and evaluate the testability design of equipment, a testability analysis method based on Bayesian network inference model is proposed in the paper. The model can adequately apply testability information and...To analyze and evaluate the testability design of equipment, a testability analysis method based on Bayesian network inference model is proposed in the paper. The model can adequately apply testability information and many uncertainty information of design and maintenance process, so it can analyze testability by and large from Bayesian inference. The detailed procedure to analyze and evaluate testability for equipments by Bayesian network is given in the paper. Its modeling process is simple, its formulation is visual, and the analysis results are more reliable than others. Examples prove that the analysis method based on Bayesian network inference can be applied to testability analysis and evaluation for complex equipments.展开更多
In order to meet the demand of testability analysis and evaluation for complex equipment under a small sample test in the equipment life cycle, the hierarchical hybrid testability model- ing and evaluation method （HH...In order to meet the demand of testability analysis and evaluation for complex equipment under a small sample test in the equipment life cycle, the hierarchical hybrid testability model- ing and evaluation method （HHTME）, which combines the testabi- lity structure model （TSM） with the testability Bayesian networks model （TBNM）, is presented. Firstly, the testability network topo- logy of complex equipment is built by using the hierarchical hybrid testability modeling method. Secondly, the prior conditional prob- ability distribution between network nodes is determined through expert experience. Then the Bayesian method is used to update the conditional probability distribution, according to history test information, virtual simulation information and similar product in- formation. Finally, the learned hierarchical hybrid testability model （HHTM） is used to estimate the testability of equipment. Compared with the results of other modeling methods, the relative deviation of the HHTM is only 0.52%, and the evaluation result is the most accu rate.展开更多
Reliability, maintainability and testability （RMT） are important properties of equipment, since they have important influ- ence on operational availability and life cycle costs （LCC）. There- fore, weighting and op...Reliability, maintainability and testability （RMT） are important properties of equipment, since they have important influ- ence on operational availability and life cycle costs （LCC）. There- fore, weighting and optimizing the three properties are of great significance. A new approach for optimization of RMT parameters is proposed. First of all, the model for the equipment operation pro- cess is established based on the generalized stochastic Petri nets （GSPN） theory. Then, by solving the GSPN model, the quantitative relationship between operational availability and RMT parameters is obtained. Afterwards, taking history data of similar equipment and operation process into consideration, a cost model of design, manufacture and maintenance is developed. Based on operational availability, the cost model and parameters ranges, an optimization model of RMT parameters is built. Finally, the effectiveness and practicability of this approach are validated through an example.展开更多
An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generatio...An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.展开更多
This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary ...This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.展开更多
In this paper, a module level fault diagnosis method is presented which considers multi-port device or subnetwork as the basic unit. The fault model in this method is quite similar to an actual condition,hence it has ...In this paper, a module level fault diagnosis method is presented which considers multi-port device or subnetwork as the basic unit. The fault model in this method is quite similar to an actual condition,hence it has practical meaning. The equations of moedule level fault diagnosis are derived, and thetestability problem for module-fault diagnosis is discussed in general. The paper then gives severaltoplolgical conditions for module-fault testubility, which are applicable to a general nonreciprocal network by introducing a generalized independent path.展开更多
This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overh...This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.展开更多
The operational readiness test(ORT),like weapon testing before firing,is becoming more and more important for systems used in the field.However,the test requirement of the ORT is distinctive.Specifically,the rule of s...The operational readiness test(ORT),like weapon testing before firing,is becoming more and more important for systems used in the field.However,the test requirement of the ORT is distinctive.Specifically,the rule of selecting test items should be changed in different test turns,and whether there is a fault is more important than where the fault is.The popular dependency matrix(D-matrix)processing algorithms becomes low efficient because they cannot change their optimizing direc-tion and spend unnecessary time on fault localization and isola-tion.To this end,this paper proposes a D-matrix processing algorithm named piecewise heuristic algorithm for D-matrix(PHAD).Its key idea is to use a piecewise function comprised of multiple different functions instead of the commonly used fixed function and switch subfunctions according to the test stage.In this manner,PHAD has the capability of changing optimizing direction,precisely matching the variant test requirements,and generating an efficient test sequence.The experiments on the random matrixes of different sizes and densities prove that the proposed algorithm performs better than the classical algo-rithms in terms of expected test cost(ETC)and other metrics.More generally,the piecewise heuristic function shows a new way to design D-matrix processing algorithm and a more flexi-ble heuristic function to meet more complicated test requirements.展开更多
To realize the requirement of diagnostic sequence optimization in the process of design for testability, the authors put forward an optimization method based on quantum-behaved particle swarm optimization （QPSO） alg...To realize the requirement of diagnostic sequence optimization in the process of design for testability, the authors put forward an optimization method based on quantum-behaved particle swarm optimization （QPSO） algorithm. By a precedence ordering coding, the diagnostic sequence optimization can be translated into a precedence ordering problem in the multidimensional space of swarm. It can get the optimizing order quickly by using the powerful and quick search capability of QPSO algorithm, and the order is the diagnostic sequence for the system. The realization of the method is simpler than other methods, and the results are more excellent than others, and it has been applied in the engineering practice.展开更多
To generate a test set for a given circuit (including both combinational and sequential circuits), choice of an algorithm within a number of existing test generation algorithms to apply is bound to vary from circuit t...To generate a test set for a given circuit (including both combinational and sequential circuits), choice of an algorithm within a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the genetic algorithms are used to construct the models of existing test generation algorithms in making such choice more easily. Therefore, we may forecast the testability parameters of a circuit before using the real test generation algorithm. The results also can be used to evaluate the efficiency of the existing test generation algorithms. Experimental results are given to convince the readers of the truth and the usefulness of this approach.展开更多
Test selection is to select the test set with the least total cost or the least total number from the alternative test set on the premise of meeting the required testability indicators.The existing models and methods ...Test selection is to select the test set with the least total cost or the least total number from the alternative test set on the premise of meeting the required testability indicators.The existing models and methods are not suitable for system level test selection.The first problem is the lack of detailed data of the units’fault set and the test set,which makes it impossible to establish a traditional dependency matrix for the system level.The second problem is that the system level fault detection rate and the fault isolation rate(referred to as"two rates")are not enough to describe the fault diagnostic ability of the system level tests.An innovative dependency matrix(called combinatorial dependency matrix)composed of three submatrices is presented.The first problem is solved by simplifying the submatrix between the units’fault and the test,and the second problem is solved by establishing the system level fault detection rate,the fault isolation rate and the integrated fault detection rate(referred to as"three rates")based on the new matrix.The mathematical model of the system level test selection problem is constructed,and the binary genetic algorithm is applied to solve the problem,which achieves the goal of system level test selection.展开更多
As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemente...As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.展开更多
基金supported by the National Natural Science Foundation of China(60771063).
文摘To analyze and evaluate the testability design of equipment, a testability analysis method based on Bayesian network inference model is proposed in the paper. The model can adequately apply testability information and many uncertainty information of design and maintenance process, so it can analyze testability by and large from Bayesian inference. The detailed procedure to analyze and evaluate testability for equipments by Bayesian network is given in the paper. Its modeling process is simple, its formulation is visual, and the analysis results are more reliable than others. Examples prove that the analysis method based on Bayesian network inference can be applied to testability analysis and evaluation for complex equipments.
基金supported by the National Defense Pre-research Foundation of China(51327030104)
文摘In order to meet the demand of testability analysis and evaluation for complex equipment under a small sample test in the equipment life cycle, the hierarchical hybrid testability model- ing and evaluation method （HHTME）, which combines the testabi- lity structure model （TSM） with the testability Bayesian networks model （TBNM）, is presented. Firstly, the testability network topo- logy of complex equipment is built by using the hierarchical hybrid testability modeling method. Secondly, the prior conditional prob- ability distribution between network nodes is determined through expert experience. Then the Bayesian method is used to update the conditional probability distribution, according to history test information, virtual simulation information and similar product in- formation. Finally, the learned hierarchical hybrid testability model （HHTM） is used to estimate the testability of equipment. Compared with the results of other modeling methods, the relative deviation of the HHTM is only 0.52%, and the evaluation result is the most accu rate.
文摘Reliability, maintainability and testability （RMT） are important properties of equipment, since they have important influ- ence on operational availability and life cycle costs （LCC）. There- fore, weighting and optimizing the three properties are of great significance. A new approach for optimization of RMT parameters is proposed. First of all, the model for the equipment operation pro- cess is established based on the generalized stochastic Petri nets （GSPN） theory. Then, by solving the GSPN model, the quantitative relationship between operational availability and RMT parameters is obtained. Afterwards, taking history data of similar equipment and operation process into consideration, a cost model of design, manufacture and maintenance is developed. Based on operational availability, the cost model and parameters ranges, an optimization model of RMT parameters is built. Finally, the effectiveness and practicability of this approach are validated through an example.
基金This project was supported by the National Natural Science Foundation of China (90407007).
文摘An efficient design-for-testability （DFT） technique is proposed to achieve low overhead for scan-based delay fault testing. Existing techniques for delay test such as skewed-load or broadside make the test generation process complex and produce lower coverage for scan-based designs as compared with non-scan designs, whereas techniques such as enhanced-scan test can make the test easy but need an extra holding latch to add substantial hardware overhead. A new tri-state holding logic is presented to replace the common holding latch in enhanced-scan test to get a substantial low hardware overhead. This scheme can achieve low delay overhead by avoiding the holding latch on the critical timing scan path. What＇s more, this method can also keep the state and signal activity in the combinational circuit from the scan during data scan-in operation to reduce the power dissipation. Experiment results on a set of ISCAS89 benchmarks show the efficiency of the proposed scheme.
文摘This paper presents a new BIST method for RTL data paths based on single-control testability, a new concept of testability. The BIST method adopts hierarchical test. Test pattern generators are placed only on primary inputs and test patterns are propagated to and fed into each module. Test responses are similarly propagated to response analyzers placed only on primary outputs. For the propagation of test patterns and test responses paths existing in the data path are utilized. The DFT method for the single-control testability is also proposed. The advantages of the proposed method are high fault coverage (for single Stuck-at faults), low hardware overhead and capability of at-speed test. Moreover, test patterns generated by test pattern generators can be fed into each module at consecutive system clocks, and thus, the BIST can also detect some faults of other fault models (e.g., transition faults and delay faults) that require consecutive application of test patterns at speed of system clock.
文摘In this paper, a module level fault diagnosis method is presented which considers multi-port device or subnetwork as the basic unit. The fault model in this method is quite similar to an actual condition,hence it has practical meaning. The equations of moedule level fault diagnosis are derived, and thetestability problem for module-fault diagnosis is discussed in general. The paper then gives severaltoplolgical conditions for module-fault testubility, which are applicable to a general nonreciprocal network by introducing a generalized independent path.
文摘This paper proposes a non-scan design-for-testability method for register-transfer level circuits where a circuit consists of a controller and a data path. It achieves complete fault efficiency with low hardware overhead and at-speed testing.
文摘The operational readiness test(ORT),like weapon testing before firing,is becoming more and more important for systems used in the field.However,the test requirement of the ORT is distinctive.Specifically,the rule of selecting test items should be changed in different test turns,and whether there is a fault is more important than where the fault is.The popular dependency matrix(D-matrix)processing algorithms becomes low efficient because they cannot change their optimizing direc-tion and spend unnecessary time on fault localization and isola-tion.To this end,this paper proposes a D-matrix processing algorithm named piecewise heuristic algorithm for D-matrix(PHAD).Its key idea is to use a piecewise function comprised of multiple different functions instead of the commonly used fixed function and switch subfunctions according to the test stage.In this manner,PHAD has the capability of changing optimizing direction,precisely matching the variant test requirements,and generating an efficient test sequence.The experiments on the random matrixes of different sizes and densities prove that the proposed algorithm performs better than the classical algo-rithms in terms of expected test cost(ETC)and other metrics.More generally,the piecewise heuristic function shows a new way to design D-matrix processing algorithm and a more flexi-ble heuristic function to meet more complicated test requirements.
基金supported by the National Natural Science Foundation of China(60771063).
文摘To realize the requirement of diagnostic sequence optimization in the process of design for testability, the authors put forward an optimization method based on quantum-behaved particle swarm optimization （QPSO） algorithm. By a precedence ordering coding, the diagnostic sequence optimization can be translated into a precedence ordering problem in the multidimensional space of swarm. It can get the optimizing order quickly by using the powerful and quick search capability of QPSO algorithm, and the order is the diagnostic sequence for the system. The realization of the method is simpler than other methods, and the results are more excellent than others, and it has been applied in the engineering practice.
基金This work was supported by National Natural Science Foundation of China (NSFC) under the grant !No. 69873030
文摘To generate a test set for a given circuit (including both combinational and sequential circuits), choice of an algorithm within a number of existing test generation algorithms to apply is bound to vary from circuit to circuit. In this paper, the genetic algorithms are used to construct the models of existing test generation algorithms in making such choice more easily. Therefore, we may forecast the testability parameters of a circuit before using the real test generation algorithm. The results also can be used to evaluate the efficiency of the existing test generation algorithms. Experimental results are given to convince the readers of the truth and the usefulness of this approach.
基金supported by the National Natural Science Foundation of China(51605482)the Equipment Pre-research Project(41403020101).
文摘Test selection is to select the test set with the least total cost or the least total number from the alternative test set on the premise of meeting the required testability indicators.The existing models and methods are not suitable for system level test selection.The first problem is the lack of detailed data of the units’fault set and the test set,which makes it impossible to establish a traditional dependency matrix for the system level.The second problem is that the system level fault detection rate and the fault isolation rate(referred to as"two rates")are not enough to describe the fault diagnostic ability of the system level tests.An innovative dependency matrix(called combinatorial dependency matrix)composed of three submatrices is presented.The first problem is solved by simplifying the submatrix between the units’fault and the test,and the second problem is solved by establishing the system level fault detection rate,the fault isolation rate and the integrated fault detection rate(referred to as"three rates")based on the new matrix.The mathematical model of the system level test selection problem is constructed,and the binary genetic algorithm is applied to solve the problem,which achieves the goal of system level test selection.
文摘As a method for testing a sequential circuit efficiently, a scan design is usually used. But, since this design has some drawbacks, a non-scan testable design should be discussed. The testable design can be implemented by enhancing controllability and observability. This paper discusses a non-scan testable design for a sequential circuit by only focusing the improvement of controllability. The proposed design modifies a circuit so that all the FFs can be directly controlled by primary input lines in a test mode. Experimental results show that we can get a good testability using this method.
