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Development of 0.50μm CMOS Integrated Circuits Technology
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作者 Yu Shan, Zhang Dingkang and Huang Chang 《Journal of Systems Engineering and Electronics》 SCIE EI CSCD 1992年第4期7-10,2,共5页
Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation ... Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation doping technology have been developed. 0.50μm. CMOS integrated circuits have been fabricated using this submicron CMOS process. 展开更多
关键词 In m CMOS Integrated Circuits technology Development of 0.50 CMOS
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Fabrication of integrated resistors in printed circuit boards 被引量:1
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作者 王守国 陈清远 《Journal of Central South University》 SCIE EI CAS 2011年第3期739-743,共5页
In order to utilize integrated passive technology in printed circuit boards (PCBs), manufacturing processing for integrated resistors by lamination method was investigated. Integrated resistors fabricated from Ohmeg... In order to utilize integrated passive technology in printed circuit boards (PCBs), manufacturing processing for integrated resistors by lamination method was investigated. Integrated resistors fabricated from Ohmega technologies in the experiment were 1 408 pieces per panel with four different patterns A, B, C and D and four resistance values of 25, 50, 75 and 100 fL Six panel per batch and four batches were performed totally. The testing was done for 960 pieces of integrated resistors randomly selected with the same size. The value distribution ranges and the relative standard deviation (RSD) show that the scatter degree of the resistance decreases with the resistor size increasing and/or with the resistance increasing. Patterns D with resistance of 75 and 100% for four patterns have the resistance value variances less than 10%. Patterns C and D with resistance of 100 Ω have the manufacturing tolerance less than 10%. The process capabilities are from about 0.6 to 1.6 for the designed testing patterns, which shows that the integrated resistors fabricated have the potential to be used in multilayer PCBs in the future. 展开更多
关键词 integrated resistors lamination method printed circuit boards integrated passive technology
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