Afuzzy controller based oni mproved Generalized-Membership-Function(GMF) algorithmfor afuel cell generationsys-tem wasintroduced.Under the demands on control in application of the converter,a Field Programmable Gate A...Afuzzy controller based oni mproved Generalized-Membership-Function(GMF) algorithmfor afuel cell generationsys-tem wasintroduced.Under the demands on control in application of the converter,a Field Programmable Gate Array(FPGA) re-alization method to manage the power flow was given.This control systembased onthe proposed modified GMF was proved to bea universal approxi mation systemin theory.The fuzzy control technique was combined with Eletronic Design Automatic(EDA)technique and a paralleling fuzzy controller was i mplemented in FPGA.Paralleling fuzzy controller based oni mproved GMF algo-rithm wasi mplemented on a Cyclone FPGA.The result of si mulation based on QuartusII confirmed the validity of the proposed method.展开更多
设计实现了一种基于片上系统现场可编程门阵列(So C FPGA)的心电信号(ECG)检测系统。系统通过具有高输入阻抗、高共模抑制比和低噪声的前置采集放大电路,实现心电信号的拾取和预处理。通过基于So C FPGA的硬件平台和移植的嵌入式Linux...设计实现了一种基于片上系统现场可编程门阵列(So C FPGA)的心电信号(ECG)检测系统。系统通过具有高输入阻抗、高共模抑制比和低噪声的前置采集放大电路,实现心电信号的拾取和预处理。通过基于So C FPGA的硬件平台和移植的嵌入式Linux开发环境的软硬协同设计方式,完成了心电信号的A/D转换、VGA显示、Micro SD卡数据存储和心电信号算法处理,能够对心电信号进行小波分析和QRS波检测,实现了对心电信号的采集、显示、存储和处理。展开更多
This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diago...This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.展开更多
文摘Afuzzy controller based oni mproved Generalized-Membership-Function(GMF) algorithmfor afuel cell generationsys-tem wasintroduced.Under the demands on control in application of the converter,a Field Programmable Gate Array(FPGA) re-alization method to manage the power flow was given.This control systembased onthe proposed modified GMF was proved to bea universal approxi mation systemin theory.The fuzzy control technique was combined with Eletronic Design Automatic(EDA)technique and a paralleling fuzzy controller was i mplemented in FPGA.Paralleling fuzzy controller based oni mproved GMF algo-rithm wasi mplemented on a Cyclone FPGA.The result of si mulation based on QuartusII confirmed the validity of the proposed method.
文摘设计实现了一种基于片上系统现场可编程门阵列(So C FPGA)的心电信号(ECG)检测系统。系统通过具有高输入阻抗、高共模抑制比和低噪声的前置采集放大电路,实现心电信号的拾取和预处理。通过基于So C FPGA的硬件平台和移植的嵌入式Linux开发环境的软硬协同设计方式,完成了心电信号的A/D转换、VGA显示、Micro SD卡数据存储和心电信号算法处理,能够对心电信号进行小波分析和QRS波检测,实现了对心电信号的采集、显示、存储和处理。
基金supported by the National Natural Science Foundation of China(11705191)the Anhui Provincial Natural Science Foundation(1808085QF180)the Natural Science Foundation of Shanghai(18ZR1443600)
文摘This paper proposes a parallel cyclic shift structure of address decoder to realize a high-throughput encoding and decoding method for irregular-quasi-cyclic low-density parity-check(IR-QC-LDPC)codes,with a dual-diagonal parity structure.A normalized min-sum algorithm(NMSA)is employed for decoding.The whole verification of the encoding and decoding algorithm is simulated with Matlab,and the code rates of 5/6 and 2/3 are selected respectively for the initial bit error ratio as 6%and 1.04%.Based on the results of simulation,multi-code rates are compatible with different basis matrices.Then the simulated algorithms of encoder and decoder are migrated and implemented on the field programmable gate array(FPGA).The 183.36 Mbps throughput of encoder and the average 27.85 Mbps decoding throughput with the initial bit error ratio 6%are realized based on FPGA.
