In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity o...In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.展开更多
The growing complexity of integrated circuits (ICs) is driving the trend of IC testing towards testing based on behavioral descriptions of register-transfer level (RTL). A behavioral description contains an algorithmi...The growing complexity of integrated circuits (ICs) is driving the trend of IC testing towards testing based on behavioral descriptions of register-transfer level (RTL). A behavioral description contains an algorithmic specification of functionality of design. It may contain little or even no information about the design’s cycle-by-cycle behavior or structural implementation. However, it usually has an interior variable to lead the process of its functional phases. This interior variable is named phase variable. The functional behavior of a digital circuit changes according to different values of a phase variable. By analyzing some ITC99 benchmark circuits, this paper presents a way to generate tests for a circuit by tracing the value change of a phase variable in the circuit.展开更多
基金supported by the National High Technology Research and Development Program of China (863 Program) (2002AA1Z1490)Specialized Research Fund for the Doctoral Program of Higher Education (20040486049)the University Cooperative Research Fund of Huawei Technology Co., Ltd
文摘In order to deal with the limitations during the register transfer level verification, a new functional verification method based on the random testing for the system-level of system-on-chip is proposed.The validity of this method is proven theoretically.Specifically, testcases are generated according to many approaches of randomization.Moreover, the testbench for the system-level verification according to the proposed method is designed by using advanced modeling language.Therefore, under the circumstances that the testbench generates testcases quickly, the hardware/software co-simulation and co-verification can be implemented and the hardware/software partitioning planning can be evaluated easily.The comparison method is put to use in the evaluation approach of the testing validity.The evaluation result indicates that the efficiency of the partition testing is better than that of the random testing only when one or more subdomains are covered over with the area of errors, although the efficiency of the random testing is generally better than that of the partition testing.The experimental result indicates that this method has a good performance in the functional coverage and the cost of testing and can discover the functional errors as soon as possible.
文摘The growing complexity of integrated circuits (ICs) is driving the trend of IC testing towards testing based on behavioral descriptions of register-transfer level (RTL). A behavioral description contains an algorithmic specification of functionality of design. It may contain little or even no information about the design’s cycle-by-cycle behavior or structural implementation. However, it usually has an interior variable to lead the process of its functional phases. This interior variable is named phase variable. The functional behavior of a digital circuit changes according to different values of a phase variable. By analyzing some ITC99 benchmark circuits, this paper presents a way to generate tests for a circuit by tracing the value change of a phase variable in the circuit.
文摘分析了 CPU,ROM,RAM 的几种故障检测方法,针对列车超速防护系统主机工作的特点,实现了系统开机时完备的主机功能级自诊断(包括关键 I/O 口)和工作中短时问的周期自检.利用主机中双 CPU 工作的特点,通过双口 RAM 通道,完成双机互检.能监视程序执行行为特征,发现单 CPU 故障或程序跑飞,并对 CPU 的执行结果进行合理性检测,提高了整个系统的故障检测覆盖率.还对故障检测覆盖平及检测代价做了评估.
