A new analytical model of high voltage silicon on insulator （SOI） thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Po...A new analytical model of high voltage silicon on insulator （SOI） thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon fihn thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1 μm which is much larger than the normal value of about 30 V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage （VB,V） are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2 μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.展开更多
In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient sig...In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient signal characteristics of a 0.18-p.m single MOS device, such as SET pulse width, pulse maximum, and collected charge, are measured and an- alyzed at wafer level. We analyze in detail the influences of supply voltage and pulse energy on the SET characteristics of the device under test （DUT）. The dependences of SET characteristics on drain-induced barrier lowering （DIBL） and the parasitic bipolar junction transistor （PBJT） are also discussed. These results provide a guide for radiation-hardened deep sub-micrometer PDSOI technology for space electronics applications.展开更多
The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage...The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.展开更多
The base-collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors （HBTs） on silicon on insulator （SOI） is split into vertical and lateral parts. This paper proposes a novel analytic...The base-collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors （HBTs） on silicon on insulator （SOI） is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector- base bias-and shows a kink as the reverse collector-base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.展开更多
This paper reports that the Si＋ self-ion-implantation are conducted on the silicon-on-insulator wafers with the 2SSi＋ doses of 7 ×1012, 1 × 1013, 4 × 1013, and 3× 1014 cm-2, respectively. After t...This paper reports that the Si＋ self-ion-implantation are conducted on the silicon-on-insulator wafers with the 2SSi＋ doses of 7 ×1012, 1 × 1013, 4 × 1013, and 3× 1014 cm-2, respectively. After the suitable annealing, these samples are characterized by using the photoluminescence technique at different recorded temperatures. Plentiful emission peaks are observed in these implanted silicon-on-insulator samples, including the unwonted intense P~ band which exhibits a great potential in the optoelectronic application. These results indicate that severe transformation of the interstitial clusters can be manipulated by the implanting dose at suitable annealing temperatures. The high critical temperatures for the photoluminescence intensity growth of the two signatures are well discussed based on the thermal ionization model of free exciton.展开更多
Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28...Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.展开更多
An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, wh...An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional（2D） Poisson＇s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage（BV） is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer（Q_（ntop）） is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.展开更多
In this paper, the effect of floating body effect （FBE） on a single event transient generation mechanism in fully depleted （FD） silicon-on-insulator （SOI） technology is investigated using three-dimensional techn...In this paper, the effect of floating body effect （FBE） on a single event transient generation mechanism in fully depleted （FD） silicon-on-insulator （SOI） technology is investigated using three-dimensional technology computer-aided design （3D- TCAD） numerical simulation. The results indicate that the main SET generation mechanism is not carder drift/diffusion but floating body effect （FBE） whether for positive or negative channel metal oxide semiconductor （PMOS or NMOS）. Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking （IS） layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.展开更多
Nitrogen ions of various doses are implanted into the buried oxide （BOX） of commercial silicon-on-insulator （SOI） materials, and subsequent annealings are carried out at various temperatures. The total dose radiat...Nitrogen ions of various doses are implanted into the buried oxide （BOX） of commercial silicon-on-insulator （SOI） materials, and subsequent annealings are carried out at various temperatures. The total dose radiation responses of the nitrogen-implanted SOI wafers are characterized by the high frequency capacitance-voltage （C-V） technique after irradi- ation using a Co-60 source. It is found that there exist relatively complex relationships between the radiation hardness of the nitrogen implanted BOX and the nitrogen implantation dose at different irradiation doses. The experimental results also suggest that a lower dose nitrogen implantation and a higher post-implantation annealing temperature are suitable for improving the radiation hardness of SOI wafer. Based on the measured C V data, secondary ion mass spectrometry （SIMS）, and Fourier transform infrared （FTIR） spectroscopy, the total dose responses of the nitrogen-implanted SOI wafers are discussed.展开更多
Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface chann...Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator （SGOI） MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects （SCE）, the drain-induced barrier-lowering （DIBL） and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.展开更多
In this paper, the authors present an analytical model for coplanar waveguide on silicon-on-insulator substrate. The four-element topological network and the conformal mapping technique are used to analyse the capacit...In this paper, the authors present an analytical model for coplanar waveguide on silicon-on-insulator substrate. The four-element topological network and the conformal mapping technique are used to analyse the capacitance and the conductance of the sandwich substrate. The validity of the model is verified by the full-wave method and the experimental data. It is found that the inductance, the resistance, the capacitance and the conductance from the analytical model show they are in good agreement with the corresponding values extracted from experimental Sparameter until 10 GHz.展开更多
In order to improve the total-dose radiation hardness of the buried oxide of separation by implanted oxygen silicon- on-insulator wafers, nitrogen ions were implanted into the buried oxide with a dose of 1016 cm-2, an...In order to improve the total-dose radiation hardness of the buried oxide of separation by implanted oxygen silicon- on-insulator wafers, nitrogen ions were implanted into the buried oxide with a dose of 1016 cm-2, and subsequent annealing was performed at 1100 ℃. The effect of annealing time on the radiation hardness of the nitrogen implanted wafers has been studied by the high frequency capacitance-voltage technique. The results suggest that the improvement of the radiation hardness of the wafers can be achieved through a shorter time annealing after nitrogen implantation. The nitrogen-implanted sample with the shortest annealing time 0.5 h shows the highest tolerance to total-dose radiation. In particular, for the 1.0 and 1.5 h annealing samples, both total dose responses were unusual. After 300-krad（Si） irradiation, both the shifts of capacitance-voltage curve reached a maximum, respectively, and then decreased with increasing total dose. In addition, the wafers were analysed by the Fourier transform infrared spectroscopy technique, and some useful results have been obtained.展开更多
Silicon germanium （SiGe） heterojunction bipolar transistor （HBT） on thin silicon-on-insulator （SOI） has recently been demonstrated and integrated into the latest SOI BiCMOS technology. The Early effect of the SO...Silicon germanium （SiGe） heterojunction bipolar transistor （HBT） on thin silicon-on-insulator （SOI） has recently been demonstrated and integrated into the latest SOI BiCMOS technology. The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion, which is different from that of a bulk counterpart. A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation. The Early voltage shows a kink with the increase of the reverse base-collector bias. Large differences are observed between SOI devices and their bulk counterparts. The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design, the simulation and the fabrication of high performance SOI SiCe devices and circuits.展开更多
The hardening of the buried oxide （BOX） layer of separation by implanted oxygen （SIMOX） silicon-on-insulator （SOI） wafers against total-dose irradiation was investigated by implanting ions into the BOX layers. T...The hardening of the buried oxide （BOX） layer of separation by implanted oxygen （SIMOX） silicon-on-insulator （SOI） wafers against total-dose irradiation was investigated by implanting ions into the BOX layers. The tolerance to total-dose irradiation of the BOX layers was characterized by the comparison of the transfer characteristics of SOI NMOS transistors before and after irradiation to a total dose of 2.7 Mrad（SiO2）. The experimental results show that the implantation of silicon ions into the BOX layer can improve the tolerance of the BOX layers to total-dose irradiation. The investigation of the mechanism of the improvement suggests that the deep electron traps introduced by silicon implantation play an important role in the remarkable improvement in radiation hardness of SIMOX SOI wafers.展开更多
An analytical expression for the co/lector resistance of a novel vertical SiGe heterojunction bipolar transistor （HBT） on thin film silicon-on-insulator （SOI） is obtained with the substrate bias effects being cons...An analytical expression for the co/lector resistance of a novel vertical SiGe heterojunction bipolar transistor （HBT） on thin film silicon-on-insulator （SOI） is obtained with the substrate bias effects being considered. The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate-collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μtm millimeter-wave SiGe SOI BiCMOS devices.展开更多
This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-...This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.展开更多
A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been...A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties （1 × 10^14 cm^-2） and low gate-leakage current （IG = 1 × 10^-3 A/cm 2@Eox = 8 MV/cm）. Analysis of the current conduction mecha- nism on the deposited Al2O3 gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim （FN） tuaneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.展开更多
Silicon on insulator with highly uniform top Si is fabricated by co-implantation of H+and He+ions. Compared with the conventional ion-slicing process with H implantation only, the co-implanted specimens whose He depth...Silicon on insulator with highly uniform top Si is fabricated by co-implantation of H+and He+ions. Compared with the conventional ion-slicing process with H implantation only, the co-implanted specimens whose He depth is deeper than H profile have the top Si layer with better uniformity after splitting. In addition, the splitting occurs at the position that the maximum concentration peak of H overlaps with the secondary concentration peak of He after annealing. It is suggested that the H/He co-implantation technology is a promising approach for fabricating fully depleted silicon on insulator.展开更多
The improved performance of a wavelength-tunable arrayed waveguide grating (AWG) is demonstrated, including the crosstalk, insertion loss and the wavelength tuning efficiency. A reduced impact of the fabrication proce...The improved performance of a wavelength-tunable arrayed waveguide grating (AWG) is demonstrated, including the crosstalk, insertion loss and the wavelength tuning efficiency. A reduced impact of the fabrication process on the AWG is achieved by the design of bi-level tapers. The wavelength tuning of the AWG is achieved according to the thermo-optic effect of silicon, and uniform heating of the silicon waveguide layer is achieved by optimizing the heater design. The fabricated AWG shows a minimum crosstalk of 16 dB, a maximum insertion loss of 3.91 dB and a wavelength tuning efficiency of 8.92 nm/W, exhibiting a ～8 dB improvement of crosstalk, ～2.1 dB improvement of insertion loss and ～5 nm/W improvement of wavelength tuning efficiency, compared to our previous reported results.展开更多
A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two o...A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two oxide trenches in the drift region and a trench gate extended to the buried oxide（BOX）.Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field（RESURF） effect.Both increase the breakdown voltage（BV）.Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop（Von）.The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss（Eoff）.The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10？3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.展开更多
基金Project supported by the National Natural Science Foundation of China (Grant No 60436030)National Laboratory of Analogue Integrated Circuits,China (Grant No 9140C090305060C09)
文摘A new analytical model of high voltage silicon on insulator （SOI） thin film devices is proposed, and a formula of silicon critical electric field is derived as a function of silicon film thickness by solving a 2D Poisson equation from an effective ionization rate, with a threshold energy taken into account for electron multiplying. Unlike a conventional silicon critical electric field that is constant and independent of silicon film thickness, the proposed silicon critical electric field increases sharply with silicon fihn thickness decreasing especially in the case of thin films, and can come to 141V/μm at a film thickness of 0.1 μm which is much larger than the normal value of about 30 V/μm. From the proposed formula of silicon critical electric field, the expressions of dielectric layer electric field and vertical breakdown voltage （VB,V） are obtained. Based on the model, an ultra thin film can be used to enhance dielectric layer electric field and so increase vertical breakdown voltage for SOI devices because of its high silicon critical electric field, and with a dielectric layer thickness of 2 μm the vertical breakdown voltages reach 852 and 300V for the silicon film thicknesses of 0.1 and 5μm, respectively. In addition, a relation between dielectric layer thickness and silicon film thickness is obtained, indicating a minimum vertical breakdown voltage that should be avoided when an SOI device is designed. 2D simulated results and some experimental results are in good agreement with analytical results.
文摘In this paper, we investigate the single event transient （SET） occurring in partially depleted silicon-on-insulator （PDSOI） metal-oxide-semiconductor （MOS） devices irradiated by pulsed laser beams. Transient signal characteristics of a 0.18-p.m single MOS device, such as SET pulse width, pulse maximum, and collected charge, are measured and an- alyzed at wafer level. We analyze in detail the influences of supply voltage and pulse energy on the SET characteristics of the device under test （DUT）. The dependences of SET characteristics on drain-induced barrier lowering （DIBL） and the parasitic bipolar junction transistor （PBJT） are also discussed. These results provide a guide for radiation-hardened deep sub-micrometer PDSOI technology for space electronics applications.
文摘The effects of source-drain underlaps on the performance of a top gate silicon nanowire on insulator transistor are studied using a three dimensional(3D) self-consistent Poisson-Schrodinger quantum simulation. Voltage-controlled tunnel barrier is the device transport physics. The off current, the on/off current ratio, and the inverse subthreshold slope are improved while the on current is degraded with underlap. The physics behind this behavior is the modulation of a tunnel barrier with underlap. The underlap primarily affects the tunneling component of drain current. About 50% contribution to the gate capacitance comes from the fringing electric fields emanating from the gate metal to the source and drain. The gate capacitance reduces with underlap, which should reduce the intrinsic switching delay and increase the intrinsic cut-off frequency. However, both the on current and the transconductance reduce with underlap, and the consequence is the increase of delay and the reduction of cut-off frequency.
基金Project supported by the National Ministries and Commissions(Grant Nos.51308040203,72105499,and6139801)
文摘The base-collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors （HBTs） on silicon on insulator （SOI） is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector- base bias-and shows a kink as the reverse collector-base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.
基金supported by the National Natural Science Foundation of China (Grant No. 10964016)the Key Project of the Chinese Ministry of Education (Grant No. 210207)the Natural Science Foundation of Yunnan University (Grant No. 2009E27Q)
文摘This paper reports that the Si＋ self-ion-implantation are conducted on the silicon-on-insulator wafers with the 2SSi＋ doses of 7 ×1012, 1 × 1013, 4 × 1013, and 3× 1014 cm-2, respectively. After the suitable annealing, these samples are characterized by using the photoluminescence technique at different recorded temperatures. Plentiful emission peaks are observed in these implanted silicon-on-insulator samples, including the unwonted intense P~ band which exhibits a great potential in the optoelectronic application. These results indicate that severe transformation of the interstitial clusters can be manipulated by the implanting dose at suitable annealing temperatures. The high critical temperatures for the photoluminescence intensity growth of the two signatures are well discussed based on the thermal ionization model of free exciton.
基金supported by the National Natural Science Foundation of China(Nos.61434007 and 61376109)
文摘Based on 3 D-TCAD simulations, single-event transient(SET) effects and charge collection mechanisms in fully depleted silicon-on-insulator(FDSOI) transistors are investigated. This work presents a comparison between28-nm technology and 0.2-lm technology to analyze the impact of strike location on SET sensitivity in FDSOI devices. Simulation results show that the most SET-sensitive region in FDSOI transistors is the drain region near the gate. An in-depth analysis shows that the bipolar amplification effect in FDSOI devices is dependent on the strike locations. In addition, when the drain contact is moved toward the drain direction, the most sensitive region drifts toward the drain and collects more charge. This provides theoretical guidance for SET hardening.
基金Project supported by the National Natural Science Foundation of China(Grant No.61376080)the Natural Science Foundation of Guangdong Province,China(Grant No.2014A030313736)the Fundamental Research Funds for the Central Universities,China(Grant No.ZYGX2013J030)
文摘An analytical model for a novel triple reduced surface field（RESURF） silicon-on-insulator（SOI） lateral doublediffused metal–oxide–semiconductor（LDMOS） field effect transistor with n-type top（N-top） layer, which can obtain a low on-state resistance, is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF SOI LDMOS is presented by solving the two-dimensional（2D） Poisson＇s equation, which can also be applied to single, double and conventional triple RESURF SOI structures. The breakdown voltage（BV） is formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of N-top layer（Q_（ntop）） is derived, which can give guidance for doping the N-top layer. All the analytical results are well verified by numerical simulation results,showing the validity of the presented model. Hence, the proposed model can be a good tool for the device designers to provide accurate first-order design schemes and physical insights into the high voltage triple RESURF SOI device with N-top layer.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61376109,61434007,and 61176030)the Advanced Research Project of National University of Defense Technology,China(Grant No.0100066314001)
文摘In this paper, the effect of floating body effect （FBE） on a single event transient generation mechanism in fully depleted （FD） silicon-on-insulator （SOI） technology is investigated using three-dimensional technology computer-aided design （3D- TCAD） numerical simulation. The results indicate that the main SET generation mechanism is not carder drift/diffusion but floating body effect （FBE） whether for positive or negative channel metal oxide semiconductor （PMOS or NMOS）. Two stacking layout designs mitigating FBE are investigated as well, and the results indicate that the in-line stacking （IS） layout can mitigate FBE completely and is area penalty saving compared with the conventional stacking layout.
文摘Nitrogen ions of various doses are implanted into the buried oxide （BOX） of commercial silicon-on-insulator （SOI） materials, and subsequent annealings are carried out at various temperatures. The total dose radiation responses of the nitrogen-implanted SOI wafers are characterized by the high frequency capacitance-voltage （C-V） technique after irradi- ation using a Co-60 source. It is found that there exist relatively complex relationships between the radiation hardness of the nitrogen implanted BOX and the nitrogen implantation dose at different irradiation doses. The experimental results also suggest that a lower dose nitrogen implantation and a higher post-implantation annealing temperature are suitable for improving the radiation hardness of SOI wafer. Based on the measured C V data, secondary ion mass spectrometry （SIMS）, and Fourier transform infrared （FTIR） spectroscopy, the total dose responses of the nitrogen-implanted SOI wafers are discussed.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60976068 and 60936005)the Cultivation Fund of the Key Scientific and Technical Innovation Project, Ministry of Education of China (Grant No. 708083)the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 200807010010)
文摘Based on the exact resultant solution of two-dimensional Poisson＇s equation in strained Si and Si1-xCex layer, a simple and accurate two-dimensional.analytical model including surface channel potential, surface channel electric field, threshold voltage and subthreshold swing for fully depleted gate stack strained Si on silicon-germanium-on-insulator （SGOI） MOSFETs has been developed. The results show that this novel structure can suppress the short channel effects （SCE）, the drain-induced barrier-lowering （DIBL） and improve the subthreshold performance in nanoelectronics application. The model is verified by numerical simulation. The model provides the basic designing guidance of gate stack strained Si on SGOI MOSFETs.
基金Project supported by the National Natural Science Foundation of China(Grant No.10775166)the Zhejiang Provincial Science Technology Foundation,China(Grant No.2008C31002)
文摘In this paper, the authors present an analytical model for coplanar waveguide on silicon-on-insulator substrate. The four-element topological network and the conformal mapping technique are used to analyse the capacitance and the conductance of the sandwich substrate. The validity of the model is verified by the full-wave method and the experimental data. It is found that the inductance, the resistance, the capacitance and the conductance from the analytical model show they are in good agreement with the corresponding values extracted from experimental Sparameter until 10 GHz.
基金Project supported by the Doctoral Science Foundation of University of Jinan
文摘In order to improve the total-dose radiation hardness of the buried oxide of separation by implanted oxygen silicon- on-insulator wafers, nitrogen ions were implanted into the buried oxide with a dose of 1016 cm-2, and subsequent annealing was performed at 1100 ℃. The effect of annealing time on the radiation hardness of the nitrogen implanted wafers has been studied by the high frequency capacitance-voltage technique. The results suggest that the improvement of the radiation hardness of the wafers can be achieved through a shorter time annealing after nitrogen implantation. The nitrogen-implanted sample with the shortest annealing time 0.5 h shows the highest tolerance to total-dose radiation. In particular, for the 1.0 and 1.5 h annealing samples, both total dose responses were unusual. After 300-krad（Si） irradiation, both the shifts of capacitance-voltage curve reached a maximum, respectively, and then decreased with increasing total dose. In addition, the wafers were analysed by the Fourier transform infrared spectroscopy technique, and some useful results have been obtained.
基金Project supported by the National Ministries and Commissions (Grant Nos. 51308040203 and 6139801)the Fundamental Research Funds for the Central Universities of China (Grant Nos. 72105499 and 72104089)the Natural Science Basic Research Plan in Shaanxi Province of China (Grant No. 2010JQ8008)
文摘Silicon germanium （SiGe） heterojunction bipolar transistor （HBT） on thin silicon-on-insulator （SOI） has recently been demonstrated and integrated into the latest SOI BiCMOS technology. The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion, which is different from that of a bulk counterpart. A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation. The Early voltage shows a kink with the increase of the reverse base-collector bias. Large differences are observed between SOI devices and their bulk counterparts. The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design, the simulation and the fabrication of high performance SOI SiCe devices and circuits.
基金Project supported by the National Fund for Distinguished Young Scholars （Grant No 59925205）, the Basic Research Program of Shanghai （Grant No 02DJ14069）, and the National Natural Science Foundation of China （Grant No 10305018）.
文摘The hardening of the buried oxide （BOX） layer of separation by implanted oxygen （SIMOX） silicon-on-insulator （SOI） wafers against total-dose irradiation was investigated by implanting ions into the BOX layers. The tolerance to total-dose irradiation of the BOX layers was characterized by the comparison of the transfer characteristics of SOI NMOS transistors before and after irradiation to a total dose of 2.7 Mrad（SiO2）. The experimental results show that the implantation of silicon ions into the BOX layer can improve the tolerance of the BOX layers to total-dose irradiation. The investigation of the mechanism of the improvement suggests that the deep electron traps introduced by silicon implantation play an important role in the remarkable improvement in radiation hardness of SIMOX SOI wafers.
基金Project supported by National Ministries and Commissions(Grant Nos.51308040203 and 6139801)the Fundamental Research Funds for the Central Universities,China(Grant Nos.72105499 and 72104089)the Natural Science Basic Research Plan in Shaanxi Province of China(Grant No.2010JQ8008)
文摘An analytical expression for the co/lector resistance of a novel vertical SiGe heterojunction bipolar transistor （HBT） on thin film silicon-on-insulator （SOI） is obtained with the substrate bias effects being considered. The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate-collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μtm millimeter-wave SiGe SOI BiCMOS devices.
基金Project supported by the National Natural Science Foundation of China (Grant No. 60906038)
文摘This paper discusses the breakdown mechanism and proposes a new simulation and test method of breakdown voltage （BV） for an ultra-high-voltage （UHV） high-side thin layer silicon-on-insulator （SOI） p-channel low-density metal- oxide semiconductor （LDMOS）. Compared with the conventional simulation method, the new one is more accordant with the actual conditions of a device that can be used in the high voltage circuit. The BV of the SOI p-channel LDMOS can be properly represented and the effect of reduced bulk field can be revealed by employing the new simulation method. Simulation results show that the off-state （on-state） BV of the SOI p-channel LDMOS can reach 741 （620） V in the 3μm-thick buried oxide layer, 50μm-length drift region, and at -400 V back-gate voltage, enabling the device to be used in a 400 V UHV integrated circuit.
基金supported by the 2010 School Fundamental Scientific Research Fund of Xidian University (Grant No. K50510250008)
文摘A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric, deposited by atomic layer deposition on tile epitaxial layer of a 4H-SiC （0001） 80N-/N＋ substrate, has been fabricated. The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics, including a high breakdown electrical field of 25 MV/cm, excellent interface properties （1 × 10^14 cm^-2） and low gate-leakage current （IG = 1 × 10^-3 A/cm 2@Eox = 8 MV/cm）. Analysis of the current conduction mecha- nism on the deposited Al2O3 gate dielectric was also systematically performed. The confirmed conduction mechanisms consisted of Fowler-Nordheim （FN） tuaneling, the Frenkel-Poole mechanism, direct tunneling and Schottky emission, and the dominant current conduction mechanism depends on the applied electrical field. When the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV, which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.
基金Supported by the National Natural Science Foundation of China under Grant No 61674159the Program of National Science and Technology Major Project under Grant No 2016ZX02301003+2 种基金the Shanghai Academic/Technology Research Leader under Grant Nos 16XD1404200 and 17XD1424500the Key Research Project of Frontier Science of Chinese Academy of Sciences under Grant No QYZDB-SSW-JSC021the Strategic Priority Research Program(B)of the Chinese Academy of Sciences under Grant No XDB30030000
文摘Silicon on insulator with highly uniform top Si is fabricated by co-implantation of H+and He+ions. Compared with the conventional ion-slicing process with H implantation only, the co-implanted specimens whose He depth is deeper than H profile have the top Si layer with better uniformity after splitting. In addition, the splitting occurs at the position that the maximum concentration peak of H overlaps with the secondary concentration peak of He after annealing. It is suggested that the H/He co-implantation technology is a promising approach for fabricating fully depleted silicon on insulator.
基金Supported by the National Key R&D Program of China under Grant No 2016YFB0402504
文摘The improved performance of a wavelength-tunable arrayed waveguide grating (AWG) is demonstrated, including the crosstalk, insertion loss and the wavelength tuning efficiency. A reduced impact of the fabrication process on the AWG is achieved by the design of bi-level tapers. The wavelength tuning of the AWG is achieved according to the thermo-optic effect of silicon, and uniform heating of the silicon waveguide layer is achieved by optimizing the heater design. The fabricated AWG shows a minimum crosstalk of 16 dB, a maximum insertion loss of 3.91 dB and a wavelength tuning efficiency of 8.92 nm/W, exhibiting a ～8 dB improvement of crosstalk, ～2.1 dB improvement of insertion loss and ～5 nm/W improvement of wavelength tuning efficiency, compared to our previous reported results.
基金Projects supported by the National Natural Science Foundation of China (Grant No. 61176069)the State Key Laboratory of Electronic Thin Films and Integrated Devices,China (Grant No. CXJJ201004)the National Key Laboratory of Analog Integrated Circuit,China (Grant No. 9140C090304110C0905)
文摘A high voltage（〉 600 V） integrable silicon-on-insulator（SOI） trench-type lateral insulated gate bipolar transistor（LIGBT） with a reduced cell-pitch is proposed.The LIGBT features multiple trenches（MTs）：two oxide trenches in the drift region and a trench gate extended to the buried oxide（BOX）.Firstly,the oxide trenches enhance electric field strength because of the lower permittivity of oxide than that of Si.Secondly,oxide trenches bring in multi-directional depletion,leading to a reshaped electric field distribution and an enhanced reduced-surface electric-field（RESURF） effect.Both increase the breakdown voltage（BV）.Thirdly,oxide trenches fold the drift region around the oxide trenches,leading to a reduced cell-pitch.Finally,the oxide trenches enhance the conductivity modulation,resulting in a high electron/hole concentration in the drift region as well as a low forward voltage drop（Von）.The oxide trenches cause a low anode-cathode capacitance,which increases the switching speed and reduces the turn-off energy loss（Eoff）.The MT SOI LIGBT exhibits a BV of 603 V at a small cell-pitch of 24 μm,a Von of 1.03 V at 100 A/cm-2,a turn-off time of 250 ns and Eoff of 4.1×10？3 mJ.The trench gate extended to BOX synchronously acts as dielectric isolation between high voltage LIGBT and low voltage circuits,simplifying the fabrication processes.
