We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinationa...We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.展开更多
The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms...The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.展开更多
文摘We present a method of test generation for acyclic sequential circuits with hold registers. A complete (100% fault efficiency) test sequence for an acyclic sequential circuit can be obtained by applying a combinational test generator to all the maximal time-expansion models (TEMs) of the circuit. We propose a class of acyclic sequential circuits for which the number of maximal TEMs is one, i.e, the maximum TEM exists. For a circuit in the class, test generation can be performed by using only the maximum TEM. The proposed class of sequential circuits with the maximum TEM properly includes several known classes of acyclic sequential circuits such as balanced structures and acyclic sequential circuits without hold registers for which test generation can be also performed by using a combinational test generator. Therefore, in general, the hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.
基金supported by National Natural Science Foundation of China under grant No.69733010.
文摘The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.
