N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering （DIBL） was 6...N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering （DIBL） was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.展开更多
Self-aligned-gate heterostructure field-effect transistor（HFET） is fabricated using a wet-etching method.Titanium nitride（TiN） is one kind of thermal stable material which can be used as the gate electrode.A Ti/Au...Self-aligned-gate heterostructure field-effect transistor（HFET） is fabricated using a wet-etching method.Titanium nitride（TiN） is one kind of thermal stable material which can be used as the gate electrode.A Ti/Au cap layer is fixed on the gate and acts as an etching mask.Then the T-shaped gate is automatically formed through over-etching the TiN layer in 30% H2O2 solution at 95 ℃.After treating the ohmic region with an inductively coupled plasma（ICP） method,an Al layer is sputtered as an ohmic electrode.The ohmic contact resistance is approximately 0.3 Ω·mm after annealing at a low-temperature of 575 ℃ in N2 ambient for 1 min.The TiN gate leakage current is only 10^-8 A after the low-temperature ohmic process.The access region length of the self-aligned-gate（SAG） HFET was reduced from 2 μm to 0.3 μm compared with that of the gate-first HFET.The output current density and transconductance of the device which has the same gate length and width are also increased.展开更多
基金Project supported by the National Natural Science Foundation of China （Grant No 60376024）.
文摘N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering （DIBL） was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET, These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.
文摘Self-aligned-gate heterostructure field-effect transistor（HFET） is fabricated using a wet-etching method.Titanium nitride（TiN） is one kind of thermal stable material which can be used as the gate electrode.A Ti/Au cap layer is fixed on the gate and acts as an etching mask.Then the T-shaped gate is automatically formed through over-etching the TiN layer in 30% H2O2 solution at 95 ℃.After treating the ohmic region with an inductively coupled plasma（ICP） method,an Al layer is sputtered as an ohmic electrode.The ohmic contact resistance is approximately 0.3 Ω·mm after annealing at a low-temperature of 575 ℃ in N2 ambient for 1 min.The TiN gate leakage current is only 10^-8 A after the low-temperature ohmic process.The access region length of the self-aligned-gate（SAG） HFET was reduced from 2 μm to 0.3 μm compared with that of the gate-first HFET.The output current density and transconductance of the device which has the same gate length and width are also increased.
