The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is present...The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is presented. It has many promising characteristics such as powerful computing capability, broad I/O bandwidth, topology flexibility, and expansibility. The parallel system performance is evaluated by practical experiment.展开更多
A novel reconfigurable hardware system which uses both muhi-DSP and FPGA to attain high performance and real-time image processing are presented. The system structure and working principle of mainly processing multi-B...A novel reconfigurable hardware system which uses both muhi-DSP and FPGA to attain high performance and real-time image processing are presented. The system structure and working principle of mainly processing multi-BSP board, extended multi-DSP board are analysed. The outstanding advantage is that the communication among different board components of this system is supported by high speed link ports ＆ serial ports for increasing the system performance and computational power. Then the implementation of embedded real-time operating systems （RTOS） by us is discussed in detail. In this system, we adopt two kinds of parallel structures controlled by RTOS for parallel processing of algorithms. The experimental results show that exploitive period of the system is short, and maintenance convenient. Thus it is suitable for real-time image processing and can get satisfactory effect of image recognition.展开更多
The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of re configurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented...The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of re configurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented. Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of 'hardware' function that can be called by the DSP in high-level algorithm. It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.展开更多
基金This project was supported by the National Natural Science Foundation of China (60135020).
文摘The flexibility of traditional image processing system is limited because those system are designed for specific applications. In this paper, a new TMS320C64x-based multi-DSP parallel computing architecture is presented. It has many promising characteristics such as powerful computing capability, broad I/O bandwidth, topology flexibility, and expansibility. The parallel system performance is evaluated by practical experiment.
基金This project was supported by the National Natural Science Foundation of China(60135020) National Key Pre-researchProject of China(413010701 -3) .
文摘A novel reconfigurable hardware system which uses both muhi-DSP and FPGA to attain high performance and real-time image processing are presented. The system structure and working principle of mainly processing multi-BSP board, extended multi-DSP board are analysed. The outstanding advantage is that the communication among different board components of this system is supported by high speed link ports ＆ serial ports for increasing the system performance and computational power. Then the implementation of embedded real-time operating systems （RTOS） by us is discussed in detail. In this system, we adopt two kinds of parallel structures controlled by RTOS for parallel processing of algorithms. The experimental results show that exploitive period of the system is short, and maintenance convenient. Thus it is suitable for real-time image processing and can get satisfactory effect of image recognition.
文摘The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of re configurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented. Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of 'hardware' function that can be called by the DSP in high-level algorithm. It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.
