A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol ...A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.展开更多
文章提出一种在片上系统(System on Chip,SoC)实现高吞吐率的有限状态熵编码(finite state entropy,FSE)算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码(Huffman coding,HC)进行性能比...文章提出一种在片上系统(System on Chip,SoC)实现高吞吐率的有限状态熵编码(finite state entropy,FSE)算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码(Huffman coding,HC)进行性能比较,结果表明,所提出的硬件FSE编码器和解码器具有显著优势。硬件FSE(hFSE)架构实现在SoC的处理系统和可编程逻辑块(programmable logic,PL)上,通过高级可扩展接口(Advanced eXtensible Interface 4,AXI4)总线连接SoC的处理系统和可编程逻辑块。算法测试显示,FSE算法在非均匀数据分布和大数据量情况下,具有更好的压缩率。该文设计的编码器和解码器已在可编程逻辑块上实现,其中包括1个可配置的缓冲模块,将比特流作为单字节或双字节配置输出到8 bit位宽4096深度或16 bit位宽2048深度的块随机访问存储器(block random access memory,BRAM)中。所提出的FSE硬件架构为实时压缩应用提供了高吞吐率、低功耗和低资源消耗的硬件实现。展开更多
设计实现了一种基于片上系统现场可编程门阵列(So C FPGA)的心电信号(ECG)检测系统。系统通过具有高输入阻抗、高共模抑制比和低噪声的前置采集放大电路,实现心电信号的拾取和预处理。通过基于So C FPGA的硬件平台和移植的嵌入式Linux...设计实现了一种基于片上系统现场可编程门阵列(So C FPGA)的心电信号(ECG)检测系统。系统通过具有高输入阻抗、高共模抑制比和低噪声的前置采集放大电路,实现心电信号的拾取和预处理。通过基于So C FPGA的硬件平台和移植的嵌入式Linux开发环境的软硬协同设计方式,完成了心电信号的A/D转换、VGA显示、Micro SD卡数据存储和心电信号算法处理,能够对心电信号进行小波分析和QRS波检测,实现了对心电信号的采集、显示、存储和处理。展开更多
随机共振作为一种新颖的信号处理手段在各个领域得到广泛应用,它的硬件实现具有重要的工程应用价值。介绍了一种便携式变步长随机共振仪,硬件采用片上系统(system on chip)作为CPU。为了同时实现FFT和随机共振算法,选用了FP-GA作为协处...随机共振作为一种新颖的信号处理手段在各个领域得到广泛应用,它的硬件实现具有重要的工程应用价值。介绍了一种便携式变步长随机共振仪,硬件采用片上系统(system on chip)作为CPU。为了同时实现FFT和随机共振算法,选用了FP-GA作为协处理器。仪器软件建立在实时操作系统基础上,使系统性能更加稳定。介绍了随机共振仪的软硬件组成,给出了仿真实例,验证了算法在随机共振仪上实现的有效性。展开更多
基金supported by the High Technology Research and Development Program of Fujian Province(2010HZ0004-1,2009HZ0003-1)
文摘A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.
文摘文章提出一种在片上系统(System on Chip,SoC)实现高吞吐率的有限状态熵编码(finite state entropy,FSE)算法。通过压缩率、速度、资源消耗、功耗4个方面对所提出的编码器和解码器与典型的硬件哈夫曼编码(Huffman coding,HC)进行性能比较,结果表明,所提出的硬件FSE编码器和解码器具有显著优势。硬件FSE(hFSE)架构实现在SoC的处理系统和可编程逻辑块(programmable logic,PL)上,通过高级可扩展接口(Advanced eXtensible Interface 4,AXI4)总线连接SoC的处理系统和可编程逻辑块。算法测试显示,FSE算法在非均匀数据分布和大数据量情况下,具有更好的压缩率。该文设计的编码器和解码器已在可编程逻辑块上实现,其中包括1个可配置的缓冲模块,将比特流作为单字节或双字节配置输出到8 bit位宽4096深度或16 bit位宽2048深度的块随机访问存储器(block random access memory,BRAM)中。所提出的FSE硬件架构为实时压缩应用提供了高吞吐率、低功耗和低资源消耗的硬件实现。
文摘设计实现了一种基于片上系统现场可编程门阵列(So C FPGA)的心电信号(ECG)检测系统。系统通过具有高输入阻抗、高共模抑制比和低噪声的前置采集放大电路,实现心电信号的拾取和预处理。通过基于So C FPGA的硬件平台和移植的嵌入式Linux开发环境的软硬协同设计方式,完成了心电信号的A/D转换、VGA显示、Micro SD卡数据存储和心电信号算法处理,能够对心电信号进行小波分析和QRS波检测,实现了对心电信号的采集、显示、存储和处理。
文摘随机共振作为一种新颖的信号处理手段在各个领域得到广泛应用,它的硬件实现具有重要的工程应用价值。介绍了一种便携式变步长随机共振仪,硬件采用片上系统(system on chip)作为CPU。为了同时实现FFT和随机共振算法,选用了FP-GA作为协处理器。仪器软件建立在实时操作系统基础上,使系统性能更加稳定。介绍了随机共振仪的软硬件组成,给出了仿真实例,验证了算法在随机共振仪上实现的有效性。
