This paper presents an approach of singular value de- composition plus digital phase lock loop to solve the difficult problem of blind pseudo-noise （PN） sequence estimation in low signal to noise ratios （SNR） dire...This paper presents an approach of singular value de- composition plus digital phase lock loop to solve the difficult problem of blind pseudo-noise （PN） sequence estimation in low signal to noise ratios （SNR） direct sequence spread spectrum （DS-SS） signals with residual carrier. This approach needs some given parameters, such as the period and code rate of PN sequence. The received signal is firstly sampled and divided into non-overlapping signal vectors according to a temporal window, whose duration is two periods of PN sequence. An autocorrelation matrix is then computed and accumulated by those signal vectors one by one. The PN sequence with residual carrier can be estimated by the principal eigenvector of the autocorrelation matrix. Further more, a digital phase lock loop is used to process the estimated PN sequence, it estimates and tracks the residual carrier and removes the residual carrier in the end. Theory analysis and computer simulation results show that this approach can effectively realize the PN sequence blind estimation from the input DS-SS signals with residual carrier in lower SNR.展开更多
This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorit...This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset（RCFO） using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop（MPLL） is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance.展开更多
A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system contr...A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.展开更多
基金supported by the National Natural Science Foundation of China (10776040 60602057)+4 种基金Program for New Century Excellent Talents in University (NCET)the Project of Key Laboratory of Signal and Information Processing of Chongqing (CSTC2009CA2003)the Natural Science Foundation of Chongqing Science and Technology Commission (CSTC2009BB2287)the Natural Science Foundation of Chongqing Municipal Education Commission (KJ060509 KJ080517)
文摘This paper presents an approach of singular value de- composition plus digital phase lock loop to solve the difficult problem of blind pseudo-noise （PN） sequence estimation in low signal to noise ratios （SNR） direct sequence spread spectrum （DS-SS） signals with residual carrier. This approach needs some given parameters, such as the period and code rate of PN sequence. The received signal is firstly sampled and divided into non-overlapping signal vectors according to a temporal window, whose duration is two periods of PN sequence. An autocorrelation matrix is then computed and accumulated by those signal vectors one by one. The PN sequence with residual carrier can be estimated by the principal eigenvector of the autocorrelation matrix. Further more, a digital phase lock loop is used to process the estimated PN sequence, it estimates and tracks the residual carrier and removes the residual carrier in the end. Theory analysis and computer simulation results show that this approach can effectively realize the PN sequence blind estimation from the input DS-SS signals with residual carrier in lower SNR.
基金supported by the National Natural Science Foundation of China(60872026)the Natural Science Foundation of Tianjin(09JCZDJC16900)
文摘This paper presents an algorithm that aims to reduce the peak-to-average power ratio（PAPR） of orthogonal frequency division multiplexing（OFDM） communication systems while maintaining frequency tracking.The algorithm achieves PAPR reduction by applying the complex conjugates of the data symbol obtained from the frequency domain to cancel the phase of the data symbol.A likelihood estimator is used to obtain the sub-carrier phase error due to the residual carrier frequency offset（RCFO） using the same complex conjugates as a pilot signal.Furthermore,a joint time and frequency domain multicarrier phase locked loop（MPLL） is developed to compensate additional frequency offset.Simulation results show that this algorithm is capable of reducing PAPR without impacting the frequency tracking performance.
基金Project(2011912004)supported by the Major Program of the Economic & Information Commission Program of Guangdong Province,ChinaProjects(2011B010700065,2011A090200106)supported by the Major Program of the Department of Science and Technology of Guangdong Province,China
文摘A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.
