A power management unit （PMU） chip supplying dual panel supply voltage, which has a low electro-magnetic interference （EMI） characteristic and is favorable for miniaturization, is designed. A two-phase charge pump...A power management unit （PMU） chip supplying dual panel supply voltage, which has a low electro-magnetic interference （EMI） characteristic and is favorable for miniaturization, is designed. A two-phase charge pump circuit using external pumping capacitor increases its pumping current and works out the charge-loss problem by using bulk-potential biasing circuit. A low-power start-up circuit is also proposed to reduce the power consumption of the band-gap reference voltage generator. And the ring oscillator used in the ELVSS power circuit is designed with logic devices by supplying the logic power supply to reduce the layout area. The PMU chip is designed with MagnaChip＇s 0.25 μ high-voltage process. The driving currents of ELVDD and ELVSS are more than 50 mA when a SPICE simulation is done.展开更多
A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:...A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.展开更多
Selective harmonic elimination(SHE) in multilevel inverters is an intricate optimization problem that involves a set of nonlinear transcendental equations which have multiple local minima. A new advanced objective fun...Selective harmonic elimination(SHE) in multilevel inverters is an intricate optimization problem that involves a set of nonlinear transcendental equations which have multiple local minima. A new advanced objective function with proper weighting is proposed and also its efficiency is compared with the objective function which is more similar to the proposed one. To enhance the ability of the SHE in eliminating high number of selected harmonics, at each level of the output voltage, one slot is created. The SHE problem is solved by imperialist competitive algorithm(ICA). The conventional SHE methods cannot eliminate the selected harmonics and satisfy the fundamental component in some ranges of modulation indexes. So, to surmount the SHE defect, a DC-DC converter is applied. Theoretical results are substantiated by simulations and experimental results for a 9-level multilevel inverter. The obtained results illustrate that the proposed method successfully minimizes a large number of identified harmonics which consequences very low total harmonic distortion of output voltage.展开更多
文摘A power management unit （PMU） chip supplying dual panel supply voltage, which has a low electro-magnetic interference （EMI） characteristic and is favorable for miniaturization, is designed. A two-phase charge pump circuit using external pumping capacitor increases its pumping current and works out the charge-loss problem by using bulk-potential biasing circuit. A low-power start-up circuit is also proposed to reduce the power consumption of the band-gap reference voltage generator. And the ring oscillator used in the ELVSS power circuit is designed with logic devices by supplying the logic power supply to reduce the layout area. The PMU chip is designed with MagnaChip＇s 0.25 μ high-voltage process. The driving currents of ELVDD and ELVSS are more than 50 mA when a SPICE simulation is done.
基金Project supported by the Second Stage of Brain Korea 21
文摘A 512-bit EEPROM IP was designed by using just logic process based devices.To limit the voltages of the devices within 5.5 V,EEPROM core circuits,control gate(CG) and tunnel gate(TG) driving circuits,DC-DC converters:positive pumping voltage(VPP=4.75 V) ,negative pumping voltage(VNN=4.75 V) ,and VNNL(=VNN/2) generation circuit were proposed.In addition,switching powers CG high voltage(CG_HV) ,CG low voltage(CG_LV) ,TG high voltage(TG_HV) ,TG low voltage(TG_LV) ,VNNL_CG and VNNL_TG switching circuit were supplied for the CG and TG driving circuit.Furthermore,a sequential pumping scheme and a new ring oscillator with a dual oscillation period were proposed.To reduce a power consumption of EEPROM in the write mode,the reference voltages VREF_VPP for VPP and VREE_VNN for VNN were used by dividing VDD(1.2 V) supply voltage supplied from the analog block in stead of removing the reference voltage generators.A voltage level detector using a capacitive divider as a low-power DC-DC converter design technique was proposed.The result shows that the power dissipation is 0.34μW in the read mode,13.76μW in the program mode,and 13.66μW in the erase mode.
文摘Selective harmonic elimination(SHE) in multilevel inverters is an intricate optimization problem that involves a set of nonlinear transcendental equations which have multiple local minima. A new advanced objective function with proper weighting is proposed and also its efficiency is compared with the objective function which is more similar to the proposed one. To enhance the ability of the SHE in eliminating high number of selected harmonics, at each level of the output voltage, one slot is created. The SHE problem is solved by imperialist competitive algorithm(ICA). The conventional SHE methods cannot eliminate the selected harmonics and satisfy the fundamental component in some ranges of modulation indexes. So, to surmount the SHE defect, a DC-DC converter is applied. Theoretical results are substantiated by simulations and experimental results for a 9-level multilevel inverter. The obtained results illustrate that the proposed method successfully minimizes a large number of identified harmonics which consequences very low total harmonic distortion of output voltage.
