Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardwar...Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardware system.This literature review focuses on calculating WCET for multi-core processors,providing a survey of traditional methods used for static and dynamic analysis and highlighting the major challenges that arise from different program execution scenarios on multi-core platforms.This paper outlines the strengths and weaknesses of current methodologies and offers insights into prospective areas of research on multi-core analysis.By presenting a comprehensive analysis of the current state of research on multi-core processor analysis for WCET estimation,this review aims to serve as a valuable resource for researchers and practitioners in the field.展开更多
为研究预应力混凝土用钢棒(steel bar for prestressed concrete, PC钢棒)-钢筋混合配筋混凝土柱的抗震性能,设计制作了5根相同尺寸、相同纵筋配筋率、不同PC钢棒替代率的PC钢棒-钢筋混合配筋混凝土柱试件,通过拟静力试验研究了PC钢棒...为研究预应力混凝土用钢棒(steel bar for prestressed concrete, PC钢棒)-钢筋混合配筋混凝土柱的抗震性能,设计制作了5根相同尺寸、相同纵筋配筋率、不同PC钢棒替代率的PC钢棒-钢筋混合配筋混凝土柱试件,通过拟静力试验研究了PC钢棒替代率对试件抗震性能的影响规律。结果表明:随着PC钢棒替代率的提高,试件的裂缝分布高度降低,裂缝数量变少,滞回曲线的饱满程度逐渐降低,耗能能力降低,残余位移角减小,自复位能力增强;当PC钢棒的替代率不大于50%时,各试件的峰值荷载接近;当PC钢棒的替代率大于50%时,试件的峰值荷载随PC钢棒替代率的增大而提高;当加载位移角相同且不大于1.0%时,配置PC钢棒的混凝土柱的残余位移角较为接近,且明显小于未配置PC钢棒的钢筋混凝土柱的残余位移角;当加载位移角相同且大于1%时,柱的残余位移角随着PC钢棒替代率的增高而降低。展开更多
A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time geneti...A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.展开更多
Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so ...Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so that the overlap of electric field distribution can be suppressed. We also propose approximate analytical solution(AAS) for κ of two crosstalk suppression models, which are two cores with one low index rod deployed in the middle and two cores with one low index rectangle trench deployed in the middle. We then do some modification for the results obtained by AAS and the modified results are proved to agree well with that obtained by finite element method(FEM). Therefore, we can use the modified AAS to get inter-core crosstalk for abovementioned two models quickly.展开更多
基金supported by ZTE Industry-University-Institute Cooperation Funds under Grant No.2022ZTE09.
文摘Real-time system timing analysis is crucial for estimating the worst-case execution time(WCET)of a program.To achieve this,static or dynamic analysis methods are used,along with targeted modeling of the actual hardware system.This literature review focuses on calculating WCET for multi-core processors,providing a survey of traditional methods used for static and dynamic analysis and highlighting the major challenges that arise from different program execution scenarios on multi-core platforms.This paper outlines the strengths and weaknesses of current methodologies and offers insights into prospective areas of research on multi-core analysis.By presenting a comprehensive analysis of the current state of research on multi-core processor analysis for WCET estimation,this review aims to serve as a valuable resource for researchers and practitioners in the field.
文摘为研究预应力混凝土用钢棒(steel bar for prestressed concrete, PC钢棒)-钢筋混合配筋混凝土柱的抗震性能,设计制作了5根相同尺寸、相同纵筋配筋率、不同PC钢棒替代率的PC钢棒-钢筋混合配筋混凝土柱试件,通过拟静力试验研究了PC钢棒替代率对试件抗震性能的影响规律。结果表明:随着PC钢棒替代率的提高,试件的裂缝分布高度降低,裂缝数量变少,滞回曲线的饱满程度逐渐降低,耗能能力降低,残余位移角减小,自复位能力增强;当PC钢棒的替代率不大于50%时,各试件的峰值荷载接近;当PC钢棒的替代率大于50%时,试件的峰值荷载随PC钢棒替代率的增大而提高;当加载位移角相同且不大于1.0%时,配置PC钢棒的混凝土柱的残余位移角较为接近,且明显小于未配置PC钢棒的钢筋混凝土柱的残余位移角;当加载位移角相同且大于1%时,柱的残余位移角随着PC钢棒替代率的增高而降低。
文摘A variation-aware task mapping approach is proposed for a multi-core network-on-chips with redundant cores, which includes both the design-time mapping and run-time scheduling algorithms. Firstly, a design-time genetic task mapping algorithm is proposed during the design stage to generate multiple task mapping solutions which cover a maximum range of chips. Then, during the run, one optimal task mapping solution is selected. Additionally, logical cores are mapped to physically available cores. Both core asymmetry and topological changes are considered in the proposed approach. Experimental results show that the performance yield of the proposed approach is 96% on average, and the communication cost, power consumption and peak temperature are all optimized without loss of performance yield.
基金supported by National B a-sic Research Program of China(Grant No.2012CB315905)National Natural Science Foundation of China(Grant No.61501027)+1 种基金China Postdoctoral Science Foundation(Grant No.2015M570934)Fundamental Research Funds for the Central Universities(Grant No.FRF-TP-15-031A1)
文摘Decreasing mode coupling coefficient(κ) is an effective approach to suppress the inter-core crosstalk. Therefore, we deploy a low index rod and rectangle trench in the middle of two neighboring cores to reduce κ so that the overlap of electric field distribution can be suppressed. We also propose approximate analytical solution(AAS) for κ of two crosstalk suppression models, which are two cores with one low index rod deployed in the middle and two cores with one low index rectangle trench deployed in the middle. We then do some modification for the results obtained by AAS and the modified results are proved to agree well with that obtained by finite element method(FEM). Therefore, we can use the modified AAS to get inter-core crosstalk for abovementioned two models quickly.
