针对分布式光纤声传感系统信号信噪比过低的问题,提出一种基于时域局部广义最大互相关熵(TLGMCC)准则联合自适应噪声完备集合经验模态分解(CEEMDAN)与提升小波变换(LWT)的优化降噪方法。首先,使用自适应噪声完备CEEMDAN对原始信号进行分...针对分布式光纤声传感系统信号信噪比过低的问题,提出一种基于时域局部广义最大互相关熵(TLGMCC)准则联合自适应噪声完备集合经验模态分解(CEEMDAN)与提升小波变换(LWT)的优化降噪方法。首先,使用自适应噪声完备CEEMDAN对原始信号进行分解,获取模态分量。接着,将原始信号与这些模态分量分割为多个时间局部片段,并计算它们对应时间局部片段的相关熵值。然后,通过LWT算法处理弱相关分量,最后重构剩余分量以完成去噪过程。实验结果表明:在5 km的传感距离和10 m的空间分辨率的条件下,系统的信噪比达到了54.36 d B,同时均方根误差降低至0.091。展开更多
Efficient reconfigurable VLSI architecture for 1-D 5/3 and 9/7 wavelet transforms adopted in JPEG2000 proposal, based on lifting scheme is proposed. The embedded decimation technique based on fold and time multiplexin...Efficient reconfigurable VLSI architecture for 1-D 5/3 and 9/7 wavelet transforms adopted in JPEG2000 proposal, based on lifting scheme is proposed. The embedded decimation technique based on fold and time multiplexing, as well as embedded boundary data extension technique, is adopted to optimize the design of the architecture. These reduce significantly the required numbers of the multipliers, adders and registers, as well as the amount of accessing external memory, and lead to decrease efficiently the hardware cost and power consumption of the design. The architecture is designed to generate an output per clock cycle, and the detailed component and the approximation of the input signal are available alternately. Experimental simulation and comparison results are presented, which demonstrate that the proposed architecture has lower hardware complexity, thus it is adapted for embedded applications. The presented architecture is simple, regular and scalable, and well suited for VLSI implementation.展开更多
文摘针对分布式光纤声传感系统信号信噪比过低的问题,提出一种基于时域局部广义最大互相关熵(TLGMCC)准则联合自适应噪声完备集合经验模态分解(CEEMDAN)与提升小波变换(LWT)的优化降噪方法。首先,使用自适应噪声完备CEEMDAN对原始信号进行分解,获取模态分量。接着,将原始信号与这些模态分量分割为多个时间局部片段,并计算它们对应时间局部片段的相关熵值。然后,通过LWT算法处理弱相关分量,最后重构剩余分量以完成去噪过程。实验结果表明:在5 km的传感距离和10 m的空间分辨率的条件下,系统的信噪比达到了54.36 d B,同时均方根误差降低至0.091。
文摘Efficient reconfigurable VLSI architecture for 1-D 5/3 and 9/7 wavelet transforms adopted in JPEG2000 proposal, based on lifting scheme is proposed. The embedded decimation technique based on fold and time multiplexing, as well as embedded boundary data extension technique, is adopted to optimize the design of the architecture. These reduce significantly the required numbers of the multipliers, adders and registers, as well as the amount of accessing external memory, and lead to decrease efficiently the hardware cost and power consumption of the design. The architecture is designed to generate an output per clock cycle, and the detailed component and the approximation of the input signal are available alternately. Experimental simulation and comparison results are presented, which demonstrate that the proposed architecture has lower hardware complexity, thus it is adapted for embedded applications. The presented architecture is simple, regular and scalable, and well suited for VLSI implementation.
