A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge...A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.展开更多
A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS pro...A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.展开更多
In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal-oxide semiconductor field-effect transistors（VDMOSFETs） subjected to negative bias tempe...In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal-oxide semiconductor field-effect transistors（VDMOSFETs） subjected to negative bias temperature（NBT）stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps（permanent component）.Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.展开更多
基金supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2010ZX02201)the National Natural Science Foundation of China (Grant No. 61176069)the National Defense Pre-Research of China (Grant No. 51308020304)
文摘A novel super-junction lateral double-diffused metal-oxide semiconductor （SJ-LDMOS） with a partial lightly doped P pillar （PD） is proposed. Firstly, the reduction in the partial P pillar charges ensures the charge balance and suppresses the substrate-assisted depletion effect. Secondly, the new electric field peak produced by the P/P junction modulates the surface electric field distribution. Both of these result in a high breakdown voltage （BV）. In addition, due to the same conduction paths, the specific on-resistance （Ron,sp） of the PD SJ-LDMOS is approximately identical to the conventional SJ-LDMOS. Simulation results indicate that the average value of the surface lateral electric field of the PD SJ-LDMOS reaches 20 V/μm at a 15 μm drift length, resulting in a BV of 300 V.
基金supported by the National Natural Science Foundation of China(Grant No.61464003)the Guangxi Natural Science Foundation,China(Grant Nos.2015GXNSFAA139300 and 2018JJA170010)
文摘A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.
基金Project supported by the Fund from the Ministry of Education,Science and Technological Development of the Republic of Serbia(Grant Nos.OI-171026 and TR-32026)the Ei PCB Factory,Ni
文摘In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal-oxide semiconductor field-effect transistors（VDMOSFETs） subjected to negative bias temperature（NBT）stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps（permanent component）.Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.
