We present the design consideration and fabrication of 4H-SiC trenched-and-implanted vertical junction field-effect transistors （TI-VJFETs）. Different design factors, including channel width, channel doping, and mes...We present the design consideration and fabrication of 4H-SiC trenched-and-implanted vertical junction field-effect transistors （TI-VJFETs）. Different design factors, including channel width, channel doping, and mesa height, are con- sidered and evaluated by numerical simulations. Based on the simulation result, normally-on and normally-off devices are fabricated. The fabricated device has a 12 μm thick drift layer with 8 × 10^15 cm^-3 N-type doping and 2.6 μm channel length. The normally-on device shows a 1.2 kV blocking capability with a minimum on-state resistance of 2.33 mΩ.cm2, while the normally-off device shows an on-state resistance of 3.85 mΩ.cm2. Both the on-state and the blocking performances of the device are close to the state-of-the-art values in this voltage range.展开更多
This paper presents the development of lateral depletion-mode n-channel 4 H-SiC junction field-effect transistors(LJFETs)using double-mesa process toward high-temperature integrated circuit(IC)applications.At room tem...This paper presents the development of lateral depletion-mode n-channel 4 H-SiC junction field-effect transistors(LJFETs)using double-mesa process toward high-temperature integrated circuit(IC)applications.At room temperature,the fabricated LJFETs show a drain-to-source saturation current of 23.03μA/μm,which corresponds to a current density of 7678 A/cm^(2).The gate-to-source parasitic resistance of 17.56 kΩ·μm is reduced to contribute only 13.49%of the on-resistance of 130.15 kΩ·μm,which helps to improve the transconductance up to 8.61μS/μm.High temperature characteristics of LJFETs were performed from room temperature to 400℃.At temperatures up to 400℃in air,it is observed that the fabricated LJFETs still show normally-on operating characteristics.The drain-to-source saturation current,transconductance and intrinsic gain at 400℃are 7.47μA/μm,2.35μS/μm and 41.35,respectively.These results show significant improvement over state-of-the-art and make them attractive for high-temperature IC applications.展开更多
Ultra-high-voltage(UHV)junction field-effect transistors(JFETs)embedded separately with the lateral NPN(JFETLNPN),and the lateral and vertical NPN(JFET-LVNPN),are demonstrated experimentally for improving the electros...Ultra-high-voltage(UHV)junction field-effect transistors(JFETs)embedded separately with the lateral NPN(JFETLNPN),and the lateral and vertical NPN(JFET-LVNPN),are demonstrated experimentally for improving the electrostatic discharge(ESD)robustness.The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-k V human body model(HBM)test.The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET.The failure analysis of the devices is performed with scanning electron microscopy,and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities.Finally,the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation,and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN,because the vertical NPN has a better electron collecting capacity.The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.展开更多
在大深度测量时,由于传统空心线圈传感器自身空心线圈和差分放大器部分引入了噪声,致使感应式磁传感器探测灵敏度降低,无法满足地质探测深度的需要。针对此问题,通过理论分析空心线圈磁传感器中空心线圈的物理结构和前置放大电路的机理...在大深度测量时,由于传统空心线圈传感器自身空心线圈和差分放大器部分引入了噪声,致使感应式磁传感器探测灵敏度降低,无法满足地质探测深度的需要。针对此问题,通过理论分析空心线圈磁传感器中空心线圈的物理结构和前置放大电路的机理,研究引入噪声的主要来源,建立基于结型场效应晶体管(JFET)的感应式磁传感器等效模型,提出一种低噪声宽带宽空心线圈磁传感器。同时,分析该模型下差分放大器的频域特性,给出磁传感器输入噪声的仿真结果。在屏蔽室内和野外试验对所研制的磁传感器性能进行测试。研究结果表明:该磁传感器的3 d B响应带宽达到42.3 k Hz,相比于磁传感器3D-3响应带宽增加了1倍。在输入噪声水平方面,其输入噪声在频率为10 k Hz时为1.97 n V/Hz1/2,较磁传感器3D-3信噪比提高了10.04 d B,为感应式磁传感器在实际项目应用提供了可靠的性能保障。展开更多
基金supported by the National High Technology Research and Development Program of China(Grant No.2011AA050401)the National Science Fundfor Distinguished Young Scholars,China(Grant No.51225701)
文摘We present the design consideration and fabrication of 4H-SiC trenched-and-implanted vertical junction field-effect transistors （TI-VJFETs）. Different design factors, including channel width, channel doping, and mesa height, are con- sidered and evaluated by numerical simulations. Based on the simulation result, normally-on and normally-off devices are fabricated. The fabricated device has a 12 μm thick drift layer with 8 × 10^15 cm^-3 N-type doping and 2.6 μm channel length. The normally-on device shows a 1.2 kV blocking capability with a minimum on-state resistance of 2.33 mΩ.cm2, while the normally-off device shows an on-state resistance of 3.85 mΩ.cm2. Both the on-state and the blocking performances of the device are close to the state-of-the-art values in this voltage range.
基金Project supported by the Key Research and Development Program of Shaanxi Province,China(Grant No.2020ZDLGY03-07)the National Science Foundation of China(Grant Nos.61774117 and 61774119)+4 种基金the Science Challenge Project(Grant No.TZ2018003)the National Key R&D Program of China(Grant No.2017YFB0102302)the Shaanxi Science&Technology Nova Program,China(Grant No.2019KJXX-029)the Key-Area Research and Development Program of Guang Dong Province,China(Grant No.2020B010170001)the Fundamental Research Funds for the Central Universities,China(Grant No.5012-20106205935)。
文摘This paper presents the development of lateral depletion-mode n-channel 4 H-SiC junction field-effect transistors(LJFETs)using double-mesa process toward high-temperature integrated circuit(IC)applications.At room temperature,the fabricated LJFETs show a drain-to-source saturation current of 23.03μA/μm,which corresponds to a current density of 7678 A/cm^(2).The gate-to-source parasitic resistance of 17.56 kΩ·μm is reduced to contribute only 13.49%of the on-resistance of 130.15 kΩ·μm,which helps to improve the transconductance up to 8.61μS/μm.High temperature characteristics of LJFETs were performed from room temperature to 400℃.At temperatures up to 400℃in air,it is observed that the fabricated LJFETs still show normally-on operating characteristics.The drain-to-source saturation current,transconductance and intrinsic gain at 400℃are 7.47μA/μm,2.35μS/μm and 41.35,respectively.These results show significant improvement over state-of-the-art and make them attractive for high-temperature IC applications.
基金the National Natural Science Foundation of China(Grant No.61504049)。
文摘Ultra-high-voltage(UHV)junction field-effect transistors(JFETs)embedded separately with the lateral NPN(JFETLNPN),and the lateral and vertical NPN(JFET-LVNPN),are demonstrated experimentally for improving the electrostatic discharge(ESD)robustness.The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-k V human body model(HBM)test.The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET.The failure analysis of the devices is performed with scanning electron microscopy,and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities.Finally,the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation,and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN,because the vertical NPN has a better electron collecting capacity.The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.
文摘在大深度测量时,由于传统空心线圈传感器自身空心线圈和差分放大器部分引入了噪声,致使感应式磁传感器探测灵敏度降低,无法满足地质探测深度的需要。针对此问题,通过理论分析空心线圈磁传感器中空心线圈的物理结构和前置放大电路的机理,研究引入噪声的主要来源,建立基于结型场效应晶体管(JFET)的感应式磁传感器等效模型,提出一种低噪声宽带宽空心线圈磁传感器。同时,分析该模型下差分放大器的频域特性,给出磁传感器输入噪声的仿真结果。在屏蔽室内和野外试验对所研制的磁传感器性能进行测试。研究结果表明:该磁传感器的3 d B响应带宽达到42.3 k Hz,相比于磁传感器3D-3响应带宽增加了1倍。在输入噪声水平方面,其输入噪声在频率为10 k Hz时为1.97 n V/Hz1/2,较磁传感器3D-3信噪比提高了10.04 d B,为感应式磁传感器在实际项目应用提供了可靠的性能保障。
