An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used...An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used for design and fabrication and physical library development of thin film submicron and deep submicron CMOS/ SOI integrated circuit.展开更多
Device physics research for submicron and deep submicron space microelectronics devices and integrated circuits will be described in three topics.1.Thin film submicron and deep submicron SOS / CMOS devices and integra...Device physics research for submicron and deep submicron space microelectronics devices and integrated circuits will be described in three topics.1.Thin film submicron and deep submicron SOS / CMOS devices and integrated circuits.2.Deep submicron LDD CMOS devices and integrated circuits.3.C band and Ku band microwave GaAs MESFET and III-V compound hetrojunction HEM T and HBT devices and integrated circuits.展开更多
SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同...SiC MOSFET因其高击穿电压、高开关速度、低导通损耗等性能优势而被广泛应用于各类电力电子变换器中。然而,由于其短路耐受时间仅为2~7μs,且随母线电压升高而缩短,快速可靠的短路保护电路已成为其推广应用的关键技术之一。为应对不同母线电压下的Si C MOSFET短路故障,文中提出一种基于漏源电压积分的自适应快速短路保护方法(drain-sourcevoltageintegration-basedadaptivefast short-circuit protection method,DSVI-AFSCPM),研究所提出的DSVI-AFSCPM在硬开关短路(hardswitchingfault,HSF)和负载短路(fault under load,FUL)条件下的保护性能,进而研究不同母线电压对DSVI-AFSCPM的作用机理。同时,探究Si CMOSFET工作温度对其响应速度的影响。最后,搭建实验平台,对所提出的DSVI-AFSCPM在发生硬开关短路和负载短路时不同母线电压、不同工作温度下的保护性能进行实验测试。实验结果表明,所提出的DSVI-AFSCPM在不同母线电压下具有良好的保护速度自适应性,即母线电压越高,短路保护速度越快,并且其响应速度受Si CMOSFET工作温度影响较小,两种短路工况下工作温度从25℃变化到125℃,短路保护时间变化不超过90 ns。因此,该文为Si CMOSFET在不同母线电压下的可靠使用提供一定技术支撑。展开更多
In order to utilize integrated passive technology in printed circuit boards （PCBs）, manufacturing processing for integrated resistors by lamination method was investigated. Integrated resistors fabricated from Ohmeg...In order to utilize integrated passive technology in printed circuit boards （PCBs）, manufacturing processing for integrated resistors by lamination method was investigated. Integrated resistors fabricated from Ohmega technologies in the experiment were 1 408 pieces per panel with four different patterns A, B, C and D and four resistance values of 25, 50, 75 and 100 fL Six panel per batch and four batches were performed totally. The testing was done for 960 pieces of integrated resistors randomly selected with the same size. The value distribution ranges and the relative standard deviation （RSD） show that the scatter degree of the resistance decreases with the resistor size increasing and/or with the resistance increasing. Patterns D with resistance of 75 and 100% for four patterns have the resistance value variances less than 10%. Patterns C and D with resistance of 100 Ω have the manufacturing tolerance less than 10%. The process capabilities are from about 0.6 to 1.6 for the designed testing patterns, which shows that the integrated resistors fabricated have the potential to be used in multilayer PCBs in the future.展开更多
针对模块化多电平换流器型高压直流输电(modular multilevel converter-high voltage direct current,MMC-HVDC)系统,提出了一种创新的换流器桥臂保护方法。首先,分析了在换流器单桥臂接地以及单相桥臂间接地情况下电流的流通路径,构建...针对模块化多电平换流器型高压直流输电(modular multilevel converter-high voltage direct current,MMC-HVDC)系统,提出了一种创新的换流器桥臂保护方法。首先,分析了在换流器单桥臂接地以及单相桥臂间接地情况下电流的流通路径,构建了等值电路,并推导了换流器闭锁前后桥臂电流的表达式。基于此,剖析了故障后三相桥臂电流之和的独有特征,提出了通过检测三相桥臂和电流的基频分量是否为零来区分桥臂内部故障与外部故障的保护策略。鉴于现有桥臂保护方法无法有效应对换流器单相桥臂间短路的问题,进一步研究了此类短路情况下的特性,发现故障相上、下桥臂电流仅包含基频分量而不含直流分量,从而制定了相应的动作判据。将三相桥臂和电流保护与单相桥臂间短路保护判据进行,能够全面识别换流器桥臂上发生的各种故障,丰富和完善了换流器桥臂的保护原理。最终,通过在MATLAB/SimulinK中搭建双极MMC-HVDC系统仿真模型验证了所提出保护方法的有效性和可靠性。展开更多
文摘An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used for design and fabrication and physical library development of thin film submicron and deep submicron CMOS/ SOI integrated circuit.
文摘Device physics research for submicron and deep submicron space microelectronics devices and integrated circuits will be described in three topics.1.Thin film submicron and deep submicron SOS / CMOS devices and integrated circuits.2.Deep submicron LDD CMOS devices and integrated circuits.3.C band and Ku band microwave GaAs MESFET and III-V compound hetrojunction HEM T and HBT devices and integrated circuits.
基金Project(041010) supported by Start-Up Foundation of Northwest University,ChinaProject(UIT/39) supported by University-Industry Collaboration Program from the Innovation and Technology Fund of Hong Kong,China
文摘In order to utilize integrated passive technology in printed circuit boards （PCBs）, manufacturing processing for integrated resistors by lamination method was investigated. Integrated resistors fabricated from Ohmega technologies in the experiment were 1 408 pieces per panel with four different patterns A, B, C and D and four resistance values of 25, 50, 75 and 100 fL Six panel per batch and four batches were performed totally. The testing was done for 960 pieces of integrated resistors randomly selected with the same size. The value distribution ranges and the relative standard deviation （RSD） show that the scatter degree of the resistance decreases with the resistor size increasing and/or with the resistance increasing. Patterns D with resistance of 75 and 100% for four patterns have the resistance value variances less than 10%. Patterns C and D with resistance of 100 Ω have the manufacturing tolerance less than 10%. The process capabilities are from about 0.6 to 1.6 for the designed testing patterns, which shows that the integrated resistors fabricated have the potential to be used in multilayer PCBs in the future.
文摘Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation doping technology have been developed. 0.50μm. CMOS integrated circuits have been fabricated using this submicron CMOS process.
文摘针对模块化多电平换流器型高压直流输电(modular multilevel converter-high voltage direct current,MMC-HVDC)系统,提出了一种创新的换流器桥臂保护方法。首先,分析了在换流器单桥臂接地以及单相桥臂间接地情况下电流的流通路径,构建了等值电路,并推导了换流器闭锁前后桥臂电流的表达式。基于此,剖析了故障后三相桥臂电流之和的独有特征,提出了通过检测三相桥臂和电流的基频分量是否为零来区分桥臂内部故障与外部故障的保护策略。鉴于现有桥臂保护方法无法有效应对换流器单相桥臂间短路的问题,进一步研究了此类短路情况下的特性,发现故障相上、下桥臂电流仅包含基频分量而不含直流分量,从而制定了相应的动作判据。将三相桥臂和电流保护与单相桥臂间短路保护判据进行,能够全面识别换流器桥臂上发生的各种故障,丰富和完善了换流器桥臂的保护原理。最终,通过在MATLAB/SimulinK中搭建双极MMC-HVDC系统仿真模型验证了所提出保护方法的有效性和可靠性。
