Device physics research for submicron and deep submicron space microelectronics devices and integrated circuits will be described in three topics.1.Thin film submicron and deep submicron SOS / CMOS devices and integra...Device physics research for submicron and deep submicron space microelectronics devices and integrated circuits will be described in three topics.1.Thin film submicron and deep submicron SOS / CMOS devices and integrated circuits.2.Deep submicron LDD CMOS devices and integrated circuits.3.C band and Ku band microwave GaAs MESFET and III-V compound hetrojunction HEM T and HBT devices and integrated circuits.展开更多
An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used...An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used for design and fabrication and physical library development of thin film submicron and deep submicron CMOS/ SOI integrated circuit.展开更多
Metalization is widely used in integrated circuit devices to connect millions of devices together. The success of metallization depends strongly on diffusion barrier technology, due to the interactions of metals with ...Metalization is widely used in integrated circuit devices to connect millions of devices together. The success of metallization depends strongly on diffusion barrier technology, due to the interactions of metals with surrounding materials. As device dimension further shrinks, diffusion barrier technology is facing more challenges and opening up new opportunities, particularly for chemical vapor deposition (CVD) process technology. CVD is attracting increased attention in advanced metallization mainly due to its capability in producing conformal thin films. In this review, we will focus our discussion on CVD processes for three most important classes of diffusion barriers: Ti, W and Ta-based diffusion banters. Examples from current literature will be examined.展开更多
This article introduces a method of achieving high polarization extinction ratio using a subwavelength grating structure on a lithium niobate thin film platform,and the chip is formed on the surface of the lithium nio...This article introduces a method of achieving high polarization extinction ratio using a subwavelength grating structure on a lithium niobate thin film platform,and the chip is formed on the surface of the lithium niobate thin film.The chip,with a length of just 20μm,achieved a measured polarization extinction ratio of 29 dB at 1550 nm wavelength.This progress not only proves the possibility of achieving a high extinction ratio on a lithium niobate thin film platform,but also offers important technical references for future work on polarization beam splitters,integrated fiber optic gyroscopes,and so on.展开更多
为了满足功率电路及系统设计对p-GaN HEMT(High Electron Mobility Transistor)器件模型的需求,本文建立了一套基于表面势计算方法的增强型p-GaN HEMT器件SPICE(Simulation Program with Integrated Circuit Emphasis)模型.根据耗尽型Ga...为了满足功率电路及系统设计对p-GaN HEMT(High Electron Mobility Transistor)器件模型的需求,本文建立了一套基于表面势计算方法的增强型p-GaN HEMT器件SPICE(Simulation Program with Integrated Circuit Emphasis)模型.根据耗尽型GaN HEMT器件和增强型p-GaN HEMT器件结构的对比,推导出p-GaN栅结构电压解析公式.考虑到p-GaN栅掺杂效应和物理机理,推导出栅电容和栅电流解析公式.同时,与基于表面势的高电子迁移率晶体管高级SPICE模型内核相结合,建立完整的增强型p-GaN HEMT功率器件的SPICE模型.将所建立的SPICE模型与实测结果进行对比验证.结果表明,所建立的模型准确实现了包括转移特性、输出特性、栅电容以及栅电流在内的p-GaN HEMT器件的电学特性.模型仿真数据与实测数据拟合度误差均小于5%.本文所提出的增强型p-GaN HEMT器件模型在进行电路设计时具有重要的应用价值.展开更多
A novel ultra-low-power readout integrated circuit(ROIC) for 1 024×1 024 ultraviolet(UV) AlGaN focal plane arrays(FPA) with 18 μm-pitch was presented. In order to optimize power consumption for UVFPA readout cir...A novel ultra-low-power readout integrated circuit(ROIC) for 1 024×1 024 ultraviolet(UV) AlGaN focal plane arrays(FPA) with 18 μm-pitch was presented. In order to optimize power consumption for UVFPA readout circuit these methods were adopted, which including single-terminal amplifier under subthreshold region as CTIA amplifier, common current source load for source follow(SF) buffer in column pixels and level shift circuits, and time-sharing tail current source for column buffer. The smallest operational current of CTIA in pixel unit is only 8.5 nA with 3.3 V power supply by using single-terminal amplifier. The ROIC has been fabricated in SMIC 0.18 μm 1P6M mixed signal process and also achieved better performances with the novel design of bias current adjustable. Furthermore, the overall power consumption of the chip is 67.3 mW at 2 MHz in 8-outputs mode by the above methods according to the experimental results.展开更多
An improved rate distortion optimization （RDO） algorithm in JPEG2000 is proposed. The proposed algorithm is suitable for integrated circuit （IC） implementation and can reduce 30% computational cost. A hardware arc...An improved rate distortion optimization （RDO） algorithm in JPEG2000 is proposed. The proposed algorithm is suitable for integrated circuit （IC） implementation and can reduce 30% computational cost. A hardware architecture which includes control unit, memory, divider, data converter is also given to implement the algorithm. The circuit based on the improved algorithm is tested on FPGAs and integrated in a JPG2000 chip codec core.展开更多
A hybrid dual wedge plasmonic(HDWP)waveguide consisting of two dielectric wedges and a diamond metal wire was proposed.The coupling between dielectric wedge waveguide mode and long-rang surface plasmon polariton mode ...A hybrid dual wedge plasmonic(HDWP)waveguide consisting of two dielectric wedges and a diamond metal wire was proposed.The coupling between dielectric wedge waveguide mode and long-rang surface plasmon polariton mode results in both low propagation loss and ultra-deep-subwavelength confinement.The HDWP waveguide achieves a normalized mode area of 2.9×10^(-3)with a moderate propagation length of 532μm or a propagation length of 3028μm with a normalized mode area of 6.2×10^(-3).The impacts of possible fabrication imperfections on the mode properties are studied.The results indicate that the HDWP waveguide is quite tolerant to fabrication errors.展开更多
文摘Device physics research for submicron and deep submicron space microelectronics devices and integrated circuits will be described in three topics.1.Thin film submicron and deep submicron SOS / CMOS devices and integrated circuits.2.Deep submicron LDD CMOS devices and integrated circuits.3.C band and Ku band microwave GaAs MESFET and III-V compound hetrojunction HEM T and HBT devices and integrated circuits.
文摘Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation doping technology have been developed. 0.50μm. CMOS integrated circuits have been fabricated using this submicron CMOS process.
文摘An 'Integrated Device and Circuit simulator' for thin film (0.05-0.2μm) submicron (0.5μm) and deep submicron (0.15, 0.25,0.35μm) CMOS/ SOI integrated circuit has been developed. This simulator has been used for design and fabrication and physical library development of thin film submicron and deep submicron CMOS/ SOI integrated circuit.
文摘Metalization is widely used in integrated circuit devices to connect millions of devices together. The success of metallization depends strongly on diffusion barrier technology, due to the interactions of metals with surrounding materials. As device dimension further shrinks, diffusion barrier technology is facing more challenges and opening up new opportunities, particularly for chemical vapor deposition (CVD) process technology. CVD is attracting increased attention in advanced metallization mainly due to its capability in producing conformal thin films. In this review, we will focus our discussion on CVD processes for three most important classes of diffusion barriers: Ti, W and Ta-based diffusion banters. Examples from current literature will be examined.
基金Supported by Beijing Natural Science Foundation(4242062)and the Youth Innovation Promotion Association,CAS(2021108)。
文摘This article introduces a method of achieving high polarization extinction ratio using a subwavelength grating structure on a lithium niobate thin film platform,and the chip is formed on the surface of the lithium niobate thin film.The chip,with a length of just 20μm,achieved a measured polarization extinction ratio of 29 dB at 1550 nm wavelength.This progress not only proves the possibility of achieving a high extinction ratio on a lithium niobate thin film platform,but also offers important technical references for future work on polarization beam splitters,integrated fiber optic gyroscopes,and so on.
文摘A novel ultra-low-power readout integrated circuit(ROIC) for 1 024×1 024 ultraviolet(UV) AlGaN focal plane arrays(FPA) with 18 μm-pitch was presented. In order to optimize power consumption for UVFPA readout circuit these methods were adopted, which including single-terminal amplifier under subthreshold region as CTIA amplifier, common current source load for source follow(SF) buffer in column pixels and level shift circuits, and time-sharing tail current source for column buffer. The smallest operational current of CTIA in pixel unit is only 8.5 nA with 3.3 V power supply by using single-terminal amplifier. The ROIC has been fabricated in SMIC 0.18 μm 1P6M mixed signal process and also achieved better performances with the novel design of bias current adjustable. Furthermore, the overall power consumption of the chip is 67.3 mW at 2 MHz in 8-outputs mode by the above methods according to the experimental results.
基金This project was supported by the National"863"High Technology Programof China (2002AA1Z1420)
文摘An improved rate distortion optimization （RDO） algorithm in JPEG2000 is proposed. The proposed algorithm is suitable for integrated circuit （IC） implementation and can reduce 30% computational cost. A hardware architecture which includes control unit, memory, divider, data converter is also given to implement the algorithm. The circuit based on the improved algorithm is tested on FPGAs and integrated in a JPG2000 chip codec core.
基金National Key Basic Research Program of China(2012CB922003)National Natural Science Foundation of China(61177053)Anhui Provincial Natural Science Foundation(1508085SMA205).
文摘A hybrid dual wedge plasmonic(HDWP)waveguide consisting of two dielectric wedges and a diamond metal wire was proposed.The coupling between dielectric wedge waveguide mode and long-rang surface plasmon polariton mode results in both low propagation loss and ultra-deep-subwavelength confinement.The HDWP waveguide achieves a normalized mode area of 2.9×10^(-3)with a moderate propagation length of 532μm or a propagation length of 3028μm with a normalized mode area of 6.2×10^(-3).The impacts of possible fabrication imperfections on the mode properties are studied.The results indicate that the HDWP waveguide is quite tolerant to fabrication errors.
