Due to the interdependency of frame synchronization(FS)and channel estimation(CE),joint FS and CE(JFSCE)schemes are proposed to enhance their functionalities and therefore boost the overall performance of wireless com...Due to the interdependency of frame synchronization(FS)and channel estimation(CE),joint FS and CE(JFSCE)schemes are proposed to enhance their functionalities and therefore boost the overall performance of wireless communication systems.Although traditional JFSCE schemes alleviate the influence between FS and CE,they show deficiencies in dealing with hardware imperfection(HI)and deterministic line-of-sight(LOS)path.To tackle this challenge,we proposed a cascaded ELM-based JFSCE to alleviate the influence of HI in the scenario of the Rician fading channel.Specifically,the conventional JFSCE method is first employed to extract the initial features,and thus forms the non-Neural Network(NN)solutions for FS and CE,respectively.Then,the ELMbased networks,named FS-NET and CE-NET,are cascaded to capture the NN solutions of FS and CE.Simulation and analysis results show that,compared with the conventional JFSCE methods,the proposed cascaded ELM-based JFSCE significantly reduces the error probability of FS and the normalized mean square error(NMSE)of CE,even against the impacts of parameter variations.展开更多
The massive connectivity and limited energy pose significant challenges to deploy the enormous devices in energy-efficient and environmentally friendly in the Internet of Things(IoT).Motivated by these challenges,this...The massive connectivity and limited energy pose significant challenges to deploy the enormous devices in energy-efficient and environmentally friendly in the Internet of Things(IoT).Motivated by these challenges,this paper investigates the energy efficiency(EE)maximization problem for downlink cooperative non-orthogonal multiple access(C-NOMA)systems with hardware impairments(HIs).The base station(BS)communicates with several users via a half-duplex(HD)amplified-and-forward(AF)relay.First,we formulate the EE maximization problem of the system under HIs by jointly optimizing transmit power and power allocated coefficient(PAC)at BS,and transmit power at the relay.The original EE maximization problem is a non-convex problem,which is challenging to give the optimal solution directly.First,we use fractional programming to convert the EE maximization problem as a series of subtraction form subproblems.Then,variable substitution and block coordinate descent(BCD)method are used to handle the sub-problems.Next,a resource allocation algorithm is proposed to maximize the EE of the systems.Finally,simulation results show that the proposed algorithm outperforms the downlink cooperative orthogonal multiple access(C-OMA)scheme.展开更多
By building a turbine charged diesel engine model and a proportional electromagnet-rack model in Matlab/Simulink and using dSPACE,a hardware-in-loop(HIL) simulation platform for the electronic governor is constructed....By building a turbine charged diesel engine model and a proportional electromagnet-rack model in Matlab/Simulink and using dSPACE,a hardware-in-loop(HIL) simulation platform for the electronic governor is constructed.A developed electronic governor is simulated in this platform.The comparison between the experiment and simulation results indicates that the built models can meet the HIL requirements.The control parameters obtained from virtual calibration and the control algorithm validated by HIL simulation can be applied in real bench experiments directly.展开更多
Although there exist a few good schemes to protect the kernel hooks of operating systems, attackers are still able to circumvent existing defense mechanisms with spurious context infonmtion. To address this challenge,...Although there exist a few good schemes to protect the kernel hooks of operating systems, attackers are still able to circumvent existing defense mechanisms with spurious context infonmtion. To address this challenge, this paper proposes a framework, called HooklMA, to detect compromised kernel hooks by using hardware debugging features. The key contribution of the work is that context information is captured from hardware instead of from relatively vulnerable kernel data. Using commodity hardware, a proof-of-concept pro- totype system of HooklMA has been developed. This prototype handles 3 082 dynamic control-flow transfers with related hooks in the kernel space. Experiments show that HooklMA is capable of detecting compomised kernel hooks caused by kernel rootkits. Performance evaluations with UnixBench indicate that runtirre overhead introduced by HooklMA is about 21.5%.展开更多
Hardware Trojan(HT) refers to a special module intentionally implanted into a chip or an electronic system. The module can be exploited by the attacker to achieve destructive functions. Unfortunately the HT is difficu...Hardware Trojan(HT) refers to a special module intentionally implanted into a chip or an electronic system. The module can be exploited by the attacker to achieve destructive functions. Unfortunately the HT is difficult to detecte due to its minimal resource occupation. In order to achieve an accurate detection with high efficiency, a HT detection method based on the electromagnetic leakage of the chip is proposed in this paper. At first, the dimensionality reduction and the feature extraction of the electromagnetic leakage signals in each group(template chip, Trojan-free chip and target chip) were realized by principal component analysis(PCA). Then, the Mahalanobis distances between the template group and the other groups were calculated. Finally, the differences between the Mahalanobis distances and the threshold were compared to determine whether the HT had been implanted into the target chip. In addition, the concept of the HT Detection Quality(HTDQ) was proposed to analyze and compare the performance of different detection methods. Our experiment results indicate that the accuracy of this detection method is 91.93%, and the time consumption is 0.042s in average, which shows a high HTDQ compared with three other methods.展开更多
The Monte Carlo(MC)simulation is regarded as the gold standard for dose calculation in brachytherapy,but it consumes a large amount of computing resources.The development of heterogeneous computing makes it possible t...The Monte Carlo(MC)simulation is regarded as the gold standard for dose calculation in brachytherapy,but it consumes a large amount of computing resources.The development of heterogeneous computing makes it possible to substantially accelerate calculations with hardware accelerators.Accordingly,this study develops a fast MC tool,called THUBrachy,which can be accelerated by several types of hardware accelerators.THUBrachy can simulate photons with energy less than 3 MeV and considers all photon interactions in the energy range.It was benchmarked against the American Association of Physicists in Medicine Task Group No.43 Report using a water phantom and validated with Geant4 using a clinical case.A performance test was conducted using the clinical case,showing that a multicore central processing unit,Intel Xeon Phi,and graphics processing unit(GPU)can efficiently accelerate the simulation.GPU-accelerated THUBrachy is the fastest version,which is 200 times faster than the serial version and approximately 500 times faster than Geant4.The proposed tool shows great potential for fast and accurate dose calculations in clinical applications.展开更多
Hardware Trojans in integrated circuit chips have the characteristics of being covert,destructive,and difficult to protect,which have seriously endangered the security of the chips themselves and the information syste...Hardware Trojans in integrated circuit chips have the characteristics of being covert,destructive,and difficult to protect,which have seriously endangered the security of the chips themselves and the information systems to which they belong.Existing solutions generally rely on passive detection techniques.In this paper,a hardware Trojans active defense mechanism is designed for network switching chips based on the principle of encryption algorithm.By encoding the data entering the chip,the argot hidden in the data cannot trigger the hardware Trojans that may exist in the chip,so that the chip can work normally even if it is implanted with a hardware Trojans.The proposed method is proved to be effective in preventing hardware Trojans with different trigger characteristics by simulation tests and practical tests on our secure switching chip.展开更多
In this paper,the spectral efficiency(SE)of an uplink hardware-constrained cell-free massive multi-input multi-output(MIMO)system with maximal ratio combining(MRC)receiver filters in the context of superimposed pilots...In this paper,the spectral efficiency(SE)of an uplink hardware-constrained cell-free massive multi-input multi-output(MIMO)system with maximal ratio combining(MRC)receiver filters in the context of superimposed pilots(SPs)is investigated.Tractable closed-form SE expressions for the considered system are derived,which share us with opportunities to explore the impacts of the hardware quality coefficient,the length of coherence interval,and the power balance factor between pilot and data signals.Numerical results indicate that the achievable SE deteriorates as the hardware quality decreases and is more susceptible to the hardware impairments at the user equipments(UEs).Besides,we observe that SPs outperform regular pilots(RPs)in terms of SE and this performance gain is heavily dependent on the values of power balance factor and coherence interval.However,the superiorities of SPs over RPs have vanished when severe hardware imperfections are considered.展开更多
For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from h...For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.展开更多
This paper investigates the system outage performance of a simultaneous wireless information and power transfer(SWIPT)based two-way decodeand-forward(DF)relay network,where potential hardware impairments(HIs)in all tr...This paper investigates the system outage performance of a simultaneous wireless information and power transfer(SWIPT)based two-way decodeand-forward(DF)relay network,where potential hardware impairments(HIs)in all transceivers are considered.After harvesting energy and decoding messages simultaneously via a power splitting scheme,the energy-limited relay node forwards the decoded information to both terminals.Each terminal combines the signals from the direct and relaying links via selection combining.We derive the system outage probability under independent but non-identically distributed Nakagami-m fading channels.It reveals an overall system ceiling(OSC)effect,i.e.,the system falls in outage if the target rate exceeds an OSC threshold that is determined by the levels of HIs.Furthermore,we derive the diversity gain of the considered network.The result reveals that when the transmission rate is below the OSC threshold,the achieved diversity gain equals the sum of the shape parameter of the direct link and the smaller shape parameter of the terminalto-relay links;otherwise,the diversity gain is zero.This is different from the amplify-and-forward(AF)strategy,under which the relaying links have no contribution to the diversity gain.Simulation results validate the analytical results and reveal that compared with the AF strategy,the SWIPT based two-way relaying links under the DF strategy are more robust to HIs and achieve a lower system outage probability.展开更多
Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security application...Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security applications in the era of internet of things(IoT).In this review article,for achieving secure hardware systems in IoT,lowpower design techniques based on emerging memristive technology for hardware security primitives/systems are presented.By reviewing the state-of-the-art in three highlighted memristive application areas,i.e.memristive non-volatile memory,memristive reconfigurable logic computing and memristive artificial intelligent computing,their application-level impacts on the novel implementations of secret key generation,crypto functions and machine learning attacks are explored,respectively.For the low-power security applications in IoT,it is essential to understand how to best realize cryptographic circuitry using memristive circuitries,and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security.This review article aims to help researchers to explore security solutions,to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs.展开更多
A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is descri...A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is described in C language provides the interface between the two. The bus interface model and the ISS are linked into a singleton program--the software simulator, which communicate with the hardware simulator through Windows sockets. The implementation of the bus interface model and the synchronization between hardware and software simulator are discussed in detail. Co-simulation control of the hardware simulator is also discussed.展开更多
A fully hardware-implemented phase calculating system for the feedback control in the lower-hybrid current drive （LHCD） experiments is presented in this paper. By taking advantages of field programmable gate array ...A fully hardware-implemented phase calculating system for the feedback control in the lower-hybrid current drive （LHCD） experiments is presented in this paper. By taking advantages of field programmable gate array （FPGA） chips with embedded digital signal processing （DSP） cores and the Matlab-aided design method, the phase calculating algorithm with a square root operation and parallel process are efficiently implemented in a single FPGA chip to complete the calculation of phase differences fast and accurately in the lower-hybrid wave （LHW） system on EAST.展开更多
This paper describes a study on the feasibility of using com-mercial off -the -shelf （COTS） hardware for telecom equip-ment. The study outlines the conditions under which COTS hardware can be utilized in a network f...This paper describes a study on the feasibility of using com-mercial off -the -shelf （COTS） hardware for telecom equip-ment. The study outlines the conditions under which COTS hardware can be utilized in a network function virtualization environment. The concept of silent -error probability is intro-duced to account for software errors and/or undetectable hard-ware failures, and is included in both the theoretical work and simulations. Silent failures are critical to overall system availability. Site -related issues are created by combined site maintenance and site failure. Site maintenance does not no-ticeably limit system availability unless there are also site fail-ures. Because the theory becomes extremely involved when site failure is introduced, simulation is used to determine the impact of those facts that constitutes the undesirable features of using COTS hardware.展开更多
Chaotic systems have been intensively studied for their roles in many applications, such as cryptography, secure communications, nonlinear controls, etc. However, the limited complexity of existing chaotic systems wea...Chaotic systems have been intensively studied for their roles in many applications, such as cryptography, secure communications, nonlinear controls, etc. However, the limited complexity of existing chaotic systems weakens chaos-based practical applications. Designing chaotic maps with high complexity is attractive. This paper proposes the exponential sine chaotification model(ESCM), a method of using the exponential sine function as a nonlinear transform model, to enhance the complexity of chaotic maps. To verify the performance of the ESCM, we firstly demonstrated it through theoretical analysis. Then, to exhibit the high efficiency and usability of ESCM, we applied ESCM to one-dimensional(1D) and multidimensional(MD) chaotic systems. The effects were examined by the Lyapunov exponent and it was found that enhanced chaotic maps have much more complicated dynamic behaviors compared to their originals. To validate the simplicity of ESCM in hardware implementation, we simulated three enhanced chaotic maps using a digital signal processor(DSP). To explore the ESCM in practical application, we applied ESCM to image encryption. The results verified that the ESCM can make previous chaos maps competitive for usage in image encryption.展开更多
We report a design and implementation of a field-programmable-gate-arrays(FPGA)based hardware platform,which is used to realize control and signal readout of trapped-ion-based multi-level quantum systems.This platform...We report a design and implementation of a field-programmable-gate-arrays(FPGA)based hardware platform,which is used to realize control and signal readout of trapped-ion-based multi-level quantum systems.This platform integrates a four-channel 2.8 Gsps@14 bits arbitrary waveform generator,a 16-channel 1 Gsps@14 bits direct-digital-synthesisbased radio-frequency generator,a 16-channel 8 ns resolution pulse generator,a 10-channel 16 bits digital-to-analogconverter module,and a 2-channel proportion integration differentiation controller.The hardware platform can be applied in the trapped-ion-based multi-level quantum systems,enabling quantum control of multi-level quantum system and highdimensional quantum simulation.The platform is scalable and more channels for control and signal readout can be implemented by utilizing more parallel duplications of the hardware.The hardware platform also has a bright future to be applied in scaled trapped-ion-based quantum systems.展开更多
Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Di...Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Distance model and the model based on the template value of power consumption in combinational logic circuit. The new model can describe the power consumption characteristics of sequential logic circuits and those of combinational logic as well. The new model can be used to improve the existing power analysis methods and detect the information leakage of power consumption. Experimental results show that, compared to CPA（Correlation Power Analysis） method, our proposed attack which adopt the combinational model is more efficient in terms of the number of required power traces.展开更多
To generate test vector sets that can efficiently activate hardware Trojans and improve probability of the hardware Trojan activation,an efficient hardware Trojan activation method is proposed based on greedy algorith...To generate test vector sets that can efficiently activate hardware Trojans and improve probability of the hardware Trojan activation,an efficient hardware Trojan activation method is proposed based on greedy algorithm for combinatorial hardware Trojans. Based on the greedy algorithm and the recursive construction method in the combination test,the method formulates appropriate and useful greedy strategy and generates test vector sets with different combinatorial correlation coefficients to activate hardware Trojans in target circuits. The experiment was carried out based on advanced encryption standard（ AES） hardware encryption circuit,different combinatorial hardware Trojans were implanted in AES as target circuits,the experiment of detecting hardware Trojans in target circuits was performed by applying the proposed method and different combinatorial hardware Trojans in target circuits were activated successfully many times in the experiment. The experimental results showthat the test vector sets generated using the proposed method could effectively activate combinatorial hardware Trojans,improve the probability of the hardware Trojan being activated,and also be applied to practice.展开更多
Object traceability based on Radio Frequency Identification(RFID)is an important capability of the Internet of Things(IoT).GS1 EPCglobal,a de-facto standard in RFID technology,develops Electronic Product Code(EPC)netw...Object traceability based on Radio Frequency Identification(RFID)is an important capability of the Internet of Things(IoT).GS1 EPCglobal,a de-facto standard in RFID technology,develops Electronic Product Code(EPC)network architecture,which mainly includes EPC Information Service(EPCIS),Object Name Service(ONS),and Discovery Service(DS).This architecture is used to capture and share standardized events representing various aspects on EPC object.However,the EPC network architecture also faces challenges;for example,the separate management of unrelated event data and master data may increase time consumption when an application extracts valuable information by combing them.A Hardware-Based Information Service(HIS)device is raised in this paper,which is installed on the specific EPC tagged object directly and this could alleviate the problem above.The HIS could store the event data and master data related to the EPC identifier centrally and the application could gain the basic information based on the data stored in the HIS without utilizing ONS,DS and EPCIS.展开更多
This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline ...This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline scheme comprised of initialization and work stage is employed to enhance the solving speed of the critical logical paths.Moreover,the pipeline scheme adopts a novel optimized hardware structure to fast complete the Mod(231-1)calculation.The function of the hardware system has been validated experimentally in detail.The hardware system shows great superiorities.Compared with the same type system in recent literatures,the logic delay reduces by 47%with an additional hardware resources of only 4 multiplexers,the throughput rate reaches 5.26 Gbps and yields at least 45%better performance,the throughput rate per unit area increases 14.8%.The hardware system provides a faster and safer encryption module for the 5G wireless network.展开更多
基金supported in part by the Sichuan Science and Technology Program(Grant No.2023YFG0316)the Industry-University Research Innovation Fund of China University(Grant No.2021ITA10016)+1 种基金the Key Scientific Research Fund of Xihua University(Grant No.Z1320929)the Special Funds of Industry Development of Sichuan Province(Grant No.zyf-2018-056).
文摘Due to the interdependency of frame synchronization(FS)and channel estimation(CE),joint FS and CE(JFSCE)schemes are proposed to enhance their functionalities and therefore boost the overall performance of wireless communication systems.Although traditional JFSCE schemes alleviate the influence between FS and CE,they show deficiencies in dealing with hardware imperfection(HI)and deterministic line-of-sight(LOS)path.To tackle this challenge,we proposed a cascaded ELM-based JFSCE to alleviate the influence of HI in the scenario of the Rician fading channel.Specifically,the conventional JFSCE method is first employed to extract the initial features,and thus forms the non-Neural Network(NN)solutions for FS and CE,respectively.Then,the ELMbased networks,named FS-NET and CE-NET,are cascaded to capture the NN solutions of FS and CE.Simulation and analysis results show that,compared with the conventional JFSCE methods,the proposed cascaded ELM-based JFSCE significantly reduces the error probability of FS and the normalized mean square error(NMSE)of CE,even against the impacts of parameter variations.
基金partially supported by the National Natural Science Foundation of China under Grant 61701064Chongqing Natural Science Foundation under Grant cstc2019jcyj-msxmX0264Sichuan Science and Technology Program under Grant 2022YFQ0017。
文摘The massive connectivity and limited energy pose significant challenges to deploy the enormous devices in energy-efficient and environmentally friendly in the Internet of Things(IoT).Motivated by these challenges,this paper investigates the energy efficiency(EE)maximization problem for downlink cooperative non-orthogonal multiple access(C-NOMA)systems with hardware impairments(HIs).The base station(BS)communicates with several users via a half-duplex(HD)amplified-and-forward(AF)relay.First,we formulate the EE maximization problem of the system under HIs by jointly optimizing transmit power and power allocated coefficient(PAC)at BS,and transmit power at the relay.The original EE maximization problem is a non-convex problem,which is challenging to give the optimal solution directly.First,we use fractional programming to convert the EE maximization problem as a series of subtraction form subproblems.Then,variable substitution and block coordinate descent(BCD)method are used to handle the sub-problems.Next,a resource allocation algorithm is proposed to maximize the EE of the systems.Finally,simulation results show that the proposed algorithm outperforms the downlink cooperative orthogonal multiple access(C-OMA)scheme.
文摘By building a turbine charged diesel engine model and a proportional electromagnet-rack model in Matlab/Simulink and using dSPACE,a hardware-in-loop(HIL) simulation platform for the electronic governor is constructed.A developed electronic governor is simulated in this platform.The comparison between the experiment and simulation results indicates that the built models can meet the HIL requirements.The control parameters obtained from virtual calibration and the control algorithm validated by HIL simulation can be applied in real bench experiments directly.
基金The authors would like to thank the anonymous reviewers for their insightful corrnlents that have helped improve the presentation of this paper. The work was supported partially by the National Natural Science Foundation of China under Grants No. 61070192, No.91018008, No. 61170240 the National High-Tech Research Development Program of China under Grant No. 2007AA01ZA14 the Natural Science Foundation of Beijing un- der Grant No. 4122041.
文摘Although there exist a few good schemes to protect the kernel hooks of operating systems, attackers are still able to circumvent existing defense mechanisms with spurious context infonmtion. To address this challenge, this paper proposes a framework, called HooklMA, to detect compromised kernel hooks by using hardware debugging features. The key contribution of the work is that context information is captured from hardware instead of from relatively vulnerable kernel data. Using commodity hardware, a proof-of-concept pro- totype system of HooklMA has been developed. This prototype handles 3 082 dynamic control-flow transfers with related hooks in the kernel space. Experiments show that HooklMA is capable of detecting compomised kernel hooks caused by kernel rootkits. Performance evaluations with UnixBench indicate that runtirre overhead introduced by HooklMA is about 21.5%.
基金supported by the Special Funds for Basic Scientific Research Business Expenses of Central Universities No. 2014GCYY0the Beijing Natural Science Foundation No. 4163076the Fundamental Research Funds for the Central Universities No. 328201801
文摘Hardware Trojan(HT) refers to a special module intentionally implanted into a chip or an electronic system. The module can be exploited by the attacker to achieve destructive functions. Unfortunately the HT is difficult to detecte due to its minimal resource occupation. In order to achieve an accurate detection with high efficiency, a HT detection method based on the electromagnetic leakage of the chip is proposed in this paper. At first, the dimensionality reduction and the feature extraction of the electromagnetic leakage signals in each group(template chip, Trojan-free chip and target chip) were realized by principal component analysis(PCA). Then, the Mahalanobis distances between the template group and the other groups were calculated. Finally, the differences between the Mahalanobis distances and the threshold were compared to determine whether the HT had been implanted into the target chip. In addition, the concept of the HT Detection Quality(HTDQ) was proposed to analyze and compare the performance of different detection methods. Our experiment results indicate that the accuracy of this detection method is 91.93%, and the time consumption is 0.042s in average, which shows a high HTDQ compared with three other methods.
基金supported by the National Natural Science Foundation of China(No.11875036)。
文摘The Monte Carlo(MC)simulation is regarded as the gold standard for dose calculation in brachytherapy,but it consumes a large amount of computing resources.The development of heterogeneous computing makes it possible to substantially accelerate calculations with hardware accelerators.Accordingly,this study develops a fast MC tool,called THUBrachy,which can be accelerated by several types of hardware accelerators.THUBrachy can simulate photons with energy less than 3 MeV and considers all photon interactions in the energy range.It was benchmarked against the American Association of Physicists in Medicine Task Group No.43 Report using a water phantom and validated with Geant4 using a clinical case.A performance test was conducted using the clinical case,showing that a multicore central processing unit,Intel Xeon Phi,and graphics processing unit(GPU)can efficiently accelerate the simulation.GPU-accelerated THUBrachy is the fastest version,which is 200 times faster than the serial version and approximately 500 times faster than Geant4.The proposed tool shows great potential for fast and accurate dose calculations in clinical applications.
文摘Hardware Trojans in integrated circuit chips have the characteristics of being covert,destructive,and difficult to protect,which have seriously endangered the security of the chips themselves and the information systems to which they belong.Existing solutions generally rely on passive detection techniques.In this paper,a hardware Trojans active defense mechanism is designed for network switching chips based on the principle of encryption algorithm.By encoding the data entering the chip,the argot hidden in the data cannot trigger the hardware Trojans that may exist in the chip,so that the chip can work normally even if it is implanted with a hardware Trojans.The proposed method is proved to be effective in preventing hardware Trojans with different trigger characteristics by simulation tests and practical tests on our secure switching chip.
基金This work was supported in part by the National Natural Science Foundation of China under Grants 62071246,61771252,61861039,and 61427801in part by the National Key Research and Development Program of China under Grants 2020YFB1806608 and 2018YFC1314903+2 种基金in part by the Jiangsu Province Special Fund Project for Transformation of Scientific and Technological Achievements under Grant BA2019058in part by the Major Natural Science Research Project of Jiangsu Higher Education Institutions under Grant 18KJA510005in part by the Postgraduate Research&Practice Innovation Program of Jiangsu Province under Grants SJKY190740 and KYCX200709.
文摘In this paper,the spectral efficiency(SE)of an uplink hardware-constrained cell-free massive multi-input multi-output(MIMO)system with maximal ratio combining(MRC)receiver filters in the context of superimposed pilots(SPs)is investigated.Tractable closed-form SE expressions for the considered system are derived,which share us with opportunities to explore the impacts of the hardware quality coefficient,the length of coherence interval,and the power balance factor between pilot and data signals.Numerical results indicate that the achievable SE deteriorates as the hardware quality decreases and is more susceptible to the hardware impairments at the user equipments(UEs).Besides,we observe that SPs outperform regular pilots(RPs)in terms of SE and this performance gain is heavily dependent on the values of power balance factor and coherence interval.However,the superiorities of SPs over RPs have vanished when severe hardware imperfections are considered.
基金supported in part by the National Key R&D Program of China(No.2019YFB1803400)。
文摘For polar codes,the performance of successive cancellation list(SCL)decoding is capable of approaching that of maximum likelihood decoding.However,the existing hardware architectures for the SCL decoding suffer from high hardware complexity due to calculating L decoding paths simultaneously,which are unfriendly to the devices with limited logical resources,such as field programmable gate arrays(FPGAs).In this paper,we propose a list-serial pipelined hardware architecture with low complexity for the SCL decoding,where the serial calculation and the pipelined operation are elegantly combined to strike a balance between the complexity and the latency.Moreover,we employ only one successive cancellation(SC)decoder core without L×L crossbars,and reduce the number of inputs of the metric sorter from 2L to L+2.Finally,the FPGA implementations show that the hardware resource consumption is significantly reduced with negligible decoding performance loss.
基金supported in part by the National Natural Science Foundation of China under Grant 62201451in part by the Young Talent fund of University Association for Science and Technology in Shaanxi under Grant 20210121+1 种基金in part by the Shaanxi provincial special fund for Technological innovation guidance(2022CGBX-29)in part by BUPT Excellent Ph.D.Students Foundation under Grant CX2022106.
文摘This paper investigates the system outage performance of a simultaneous wireless information and power transfer(SWIPT)based two-way decodeand-forward(DF)relay network,where potential hardware impairments(HIs)in all transceivers are considered.After harvesting energy and decoding messages simultaneously via a power splitting scheme,the energy-limited relay node forwards the decoded information to both terminals.Each terminal combines the signals from the direct and relaying links via selection combining.We derive the system outage probability under independent but non-identically distributed Nakagami-m fading channels.It reveals an overall system ceiling(OSC)effect,i.e.,the system falls in outage if the target rate exceeds an OSC threshold that is determined by the levels of HIs.Furthermore,we derive the diversity gain of the considered network.The result reveals that when the transmission rate is below the OSC threshold,the achieved diversity gain equals the sum of the shape parameter of the direct link and the smaller shape parameter of the terminalto-relay links;otherwise,the diversity gain is zero.This is different from the amplify-and-forward(AF)strategy,under which the relaying links have no contribution to the diversity gain.Simulation results validate the analytical results and reveal that compared with the AF strategy,the SWIPT based two-way relaying links under the DF strategy are more robust to HIs and achieve a lower system outage probability.
基金supported by the DFG(German Research Foundation)Priority Program Nano Security,Project MemCrypto(Projektnummer 439827659/funding id DU 1896/2–1,PO 1220/15–1)the funding by the Fraunhofer Internal Programs under Grant No.Attract 600768。
文摘Emerging memristive devices offer enormous advantages for applications such as non-volatile memories and inmemory computing(IMC),but there is a rising interest in using memristive technologies for security applications in the era of internet of things(IoT).In this review article,for achieving secure hardware systems in IoT,lowpower design techniques based on emerging memristive technology for hardware security primitives/systems are presented.By reviewing the state-of-the-art in three highlighted memristive application areas,i.e.memristive non-volatile memory,memristive reconfigurable logic computing and memristive artificial intelligent computing,their application-level impacts on the novel implementations of secret key generation,crypto functions and machine learning attacks are explored,respectively.For the low-power security applications in IoT,it is essential to understand how to best realize cryptographic circuitry using memristive circuitries,and to assess the implications of memristive crypto implementations on security and to develop novel computing paradigms that will enhance their security.This review article aims to help researchers to explore security solutions,to analyze new possible threats and to develop corresponding protections for the secure hardware systems based on low-cost memristive circuit designs.
文摘A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is described in C language provides the interface between the two. The bus interface model and the ISS are linked into a singleton program--the software simulator, which communicate with the hardware simulator through Windows sockets. The implementation of the bus interface model and the synchronization between hardware and software simulator are discussed in detail. Co-simulation control of the hardware simulator is also discussed.
文摘A fully hardware-implemented phase calculating system for the feedback control in the lower-hybrid current drive （LHCD） experiments is presented in this paper. By taking advantages of field programmable gate array （FPGA） chips with embedded digital signal processing （DSP） cores and the Matlab-aided design method, the phase calculating algorithm with a square root operation and parallel process are efficiently implemented in a single FPGA chip to complete the calculation of phase differences fast and accurately in the lower-hybrid wave （LHW） system on EAST.
文摘This paper describes a study on the feasibility of using com-mercial off -the -shelf （COTS） hardware for telecom equip-ment. The study outlines the conditions under which COTS hardware can be utilized in a network function virtualization environment. The concept of silent -error probability is intro-duced to account for software errors and/or undetectable hard-ware failures, and is included in both the theoretical work and simulations. Silent failures are critical to overall system availability. Site -related issues are created by combined site maintenance and site failure. Site maintenance does not no-ticeably limit system availability unless there are also site fail-ures. Because the theory becomes extremely involved when site failure is introduced, simulation is used to determine the impact of those facts that constitutes the undesirable features of using COTS hardware.
基金Project supported by the National Natural Science Foundation of China (Grant No. 51507023)Chongqing Municipal Natural Science Foundation (Grant No. cstc2020jcyjmsxm X0726)the Science and Technology Research Program of Chongqing Municipal Education Commission (Grant No. KJZD-K202100506)。
文摘Chaotic systems have been intensively studied for their roles in many applications, such as cryptography, secure communications, nonlinear controls, etc. However, the limited complexity of existing chaotic systems weakens chaos-based practical applications. Designing chaotic maps with high complexity is attractive. This paper proposes the exponential sine chaotification model(ESCM), a method of using the exponential sine function as a nonlinear transform model, to enhance the complexity of chaotic maps. To verify the performance of the ESCM, we firstly demonstrated it through theoretical analysis. Then, to exhibit the high efficiency and usability of ESCM, we applied ESCM to one-dimensional(1D) and multidimensional(MD) chaotic systems. The effects were examined by the Lyapunov exponent and it was found that enhanced chaotic maps have much more complicated dynamic behaviors compared to their originals. To validate the simplicity of ESCM in hardware implementation, we simulated three enhanced chaotic maps using a digital signal processor(DSP). To explore the ESCM in practical application, we applied ESCM to image encryption. The results verified that the ESCM can make previous chaos maps competitive for usage in image encryption.
基金the Strategic Priority Research Program of CAS(Grant No.XDC07020200)the National Key R&D Program of China(Grants No.2018YFA0306600)+5 种基金the National Natural Science Foundation of China(Grant Nos.11974330 and 92165206)the Chinese Academy of Sciences(Grant No.QYZDY-SSW-SLH004)the Innovation Program for Quantum Science and Technology(Grant Nos.2021ZD0302200 and 2021ZD0301603)the Anhui Initiative in Quantum Information Technologies(Grant No.AHY050000)the Hefei Comprehensive National Science Centerthe Fundamental Research Funds for the Central Universities。
文摘We report a design and implementation of a field-programmable-gate-arrays(FPGA)based hardware platform,which is used to realize control and signal readout of trapped-ion-based multi-level quantum systems.This platform integrates a four-channel 2.8 Gsps@14 bits arbitrary waveform generator,a 16-channel 1 Gsps@14 bits direct-digital-synthesisbased radio-frequency generator,a 16-channel 8 ns resolution pulse generator,a 10-channel 16 bits digital-to-analogconverter module,and a 2-channel proportion integration differentiation controller.The hardware platform can be applied in the trapped-ion-based multi-level quantum systems,enabling quantum control of multi-level quantum system and highdimensional quantum simulation.The platform is scalable and more channels for control and signal readout can be implemented by utilizing more parallel duplications of the hardware.The hardware platform also has a bright future to be applied in scaled trapped-ion-based quantum systems.
基金supported by Major State Basic Research Development Program(No. 2013CB338004)National Natural Science Foundation of China(No.61402286, 61202372,61202371,61309021)National Science and Technology Major Project of the Ministry of Science and Technology of China (No.2014ZX01032401-001)
文摘Power analysis is a non-invaslve attack against cryptographic hardware, which effectively exploits runtime power consumption characteristics of circuits. This paper proposes a new power model which combines Hamming Distance model and the model based on the template value of power consumption in combinational logic circuit. The new model can describe the power consumption characteristics of sequential logic circuits and those of combinational logic as well. The new model can be used to improve the existing power analysis methods and detect the information leakage of power consumption. Experimental results show that, compared to CPA（Correlation Power Analysis） method, our proposed attack which adopt the combinational model is more efficient in terms of the number of required power traces.
文摘To generate test vector sets that can efficiently activate hardware Trojans and improve probability of the hardware Trojan activation,an efficient hardware Trojan activation method is proposed based on greedy algorithm for combinatorial hardware Trojans. Based on the greedy algorithm and the recursive construction method in the combination test,the method formulates appropriate and useful greedy strategy and generates test vector sets with different combinatorial correlation coefficients to activate hardware Trojans in target circuits. The experiment was carried out based on advanced encryption standard（ AES） hardware encryption circuit,different combinatorial hardware Trojans were implanted in AES as target circuits,the experiment of detecting hardware Trojans in target circuits was performed by applying the proposed method and different combinatorial hardware Trojans in target circuits were activated successfully many times in the experiment. The experimental results showthat the test vector sets generated using the proposed method could effectively activate combinatorial hardware Trojans,improve the probability of the hardware Trojan being activated,and also be applied to practice.
基金supported by the 2018 Industrial Internet Innovation and Development Project--Industrial Internet Identification Resolution System National Top-Level Node Construction Project (PhaseⅠ)
文摘Object traceability based on Radio Frequency Identification(RFID)is an important capability of the Internet of Things(IoT).GS1 EPCglobal,a de-facto standard in RFID technology,develops Electronic Product Code(EPC)network architecture,which mainly includes EPC Information Service(EPCIS),Object Name Service(ONS),and Discovery Service(DS).This architecture is used to capture and share standardized events representing various aspects on EPC object.However,the EPC network architecture also faces challenges;for example,the separate management of unrelated event data and master data may increase time consumption when an application extracts valuable information by combing them.A Hardware-Based Information Service(HIS)device is raised in this paper,which is installed on the specific EPC tagged object directly and this could alleviate the problem above.The HIS could store the event data and master data related to the EPC identifier centrally and the application could gain the basic information based on the data stored in the HIS without utilizing ONS,DS and EPCIS.
基金supported in part by the National R&D Program for Major Research Instruments of China(Grant No:62027814)the National Natural Science Foundation of China(Grant No:62104054)+2 种基金the Natural Science Foundation of Heilongjiang Province(Grant No:F2018010)the Postdoctoral Science Foundation of Heilongjiang Province,China(No:LBH-Z20133)the Fundamental Research Funds for The Central Universities,China(3072021CF0806)。
文摘This paper presents a ZUC-256 stream cipher algorithm hardware system in order to prevent the advanced security threats for 5 G wireless network.The main innovation of the hardware system is that a six-stage pipeline scheme comprised of initialization and work stage is employed to enhance the solving speed of the critical logical paths.Moreover,the pipeline scheme adopts a novel optimized hardware structure to fast complete the Mod(231-1)calculation.The function of the hardware system has been validated experimentally in detail.The hardware system shows great superiorities.Compared with the same type system in recent literatures,the logic delay reduces by 47%with an additional hardware resources of only 4 multiplexers,the throughput rate reaches 5.26 Gbps and yields at least 45%better performance,the throughput rate per unit area increases 14.8%.The hardware system provides a faster and safer encryption module for the 5G wireless network.
