In this paper, an efficient thermal analysis method is presented for large scale compound semiconductor integrated circuits based on a heterojunction bipolar transistor with considering the change of thermal conductiv...In this paper, an efficient thermal analysis method is presented for large scale compound semiconductor integrated circuits based on a heterojunction bipolar transistor with considering the change of thermal conductivity with temperature.The influence caused by the thermal conductivity can be equivalent to the increment of the local temperature surrounding the individual device. The junction temperature for each device can be efficiently calculated by the combination of the semianalytic temperature distribution function and the iteration of local temperature with high accuracy, providing a temperature distribution for a full chip. Applying this method to the InP frequency divider chip and the GaAs analog to digital converter chip, the computational results well agree with the results from the simulator COMSOL and the infrared thermal imager respectively. The proposed method can also be applied to thermal analysis in various kinds of semiconductor integrated circuits.展开更多
A scanning and uniform array architecture with large spacing,low complexity and high scalability is presented for high integration massive array applications.It is constructed by offset phase center elements arranged ...A scanning and uniform array architecture with large spacing,low complexity and high scalability is presented for high integration massive array applications.It is constructed by offset phase center elements arranged in a uniform and regular way,but its spacing can be larger than that of traditional arrays.An ideal model of the offset phase center element is established and its far-field distribution is derived.To suppress grating lobes,the phase center of any element is designed to be movable without changing its physical position.Using genetic algorithm(GA),a new constraint condition limiting the number of phase center changes is proposed to solve the objective function of the minimum values of grating lobes(GLs)and side lobes(SLs).It is shown that the optimal results can be achieved by two changes of phase centers.A multimode circular patch is developed and designed,and characteristics of the offset phase center are analyzed and verified.A prototype array of 12×12 offset phase center elements is implemented based on multi-mode circular patches.Full wave simulation results of radiation patterns show that the level of grating lobes is suppressed at least 7dB with 1.12λ spacing,while the scanning angle is 20°.展开更多
Particle accelerators are indispensable tools in both science and industry.However,the size and cost of conventional RF accelerators limits the utility and scope of this technology.Recent research has shown that a die...Particle accelerators are indispensable tools in both science and industry.However,the size and cost of conventional RF accelerators limits the utility and scope of this technology.Recent research has shown that a dielectric laser accelerator(DLA)made of dielectric structures and driven at optical frequencies can generate particle beams with energies ranging from MeV to GeV at the tabletop level.To design DLA structures with a high acceleration gradient,we demonstrate topology optimization,which is a method used to optimize the material distribution in a specific area based on given load conditions,constraints,and performance indicators.To demonstrate the effectiveness of this approach,we propose two schemes and design several acceleration structures based on them.The optimization results demonstrate that the proposed method can be applied to structure optimization for on-chip integrated laser accelerators,producing manufacturable structures with significantly improved performance compared with previous size or shape optimization methods.These results provide new physical approaches to explore ultrafast dynamics in matter,with important implications for future laser particle accelerators based on photonic chips.展开更多
底栏栅式渠首是新疆粗颗粒山溪性河流引水防沙枢纽的首选类型,但实践运用表明,当引水量超过30 m 3/s时,渠首冲沙有利、工程布置紧凑的优势逐渐丧失,后期运行管理效益大打折扣。为此在保留原有布置优势的情况下,以扩大底栏栅引水流量为目...底栏栅式渠首是新疆粗颗粒山溪性河流引水防沙枢纽的首选类型,但实践运用表明,当引水量超过30 m 3/s时,渠首冲沙有利、工程布置紧凑的优势逐渐丧失,后期运行管理效益大打折扣。为此在保留原有布置优势的情况下,以扩大底栏栅引水流量为目标,提出了“⊥”型廊道新结构及优化布置方案,新结构在原垂直水流方向“—”型廊道结构基础上增设了顺水流方向“|”型廊道(根据流量的大小可布置双排甚至多排“|”型廊道),并结合底栏栅水流动力方程及取水流量计算方法得到了“⊥”型廊道取水流量的计算方法。随后以新疆头屯河渠首为例,在保持原平面布置不变的情况下引入“⊥”型廊道新结构,其引水量可达48.96 m 3/s,提升了39.89%,工程造价降低了63.46%。“⊥”型廊道新结构及布置方案突破了传统底栏栅式渠首设计引水流量相对较小的限制,拓宽了底栏栅式渠首的适用范围,还提高了经济效益,可为此类工程提供新的工程方案。展开更多
基金Project supported by the Advance Research Foundation of China(Grant No.9140Axxx501)the National Defense Advance Research Project,China(Grant No.3151xxxx301)+1 种基金the Frontier Innovation Program,China(Grant No.48xx4)the 111 Project,China(Grant No.B12026)
文摘In this paper, an efficient thermal analysis method is presented for large scale compound semiconductor integrated circuits based on a heterojunction bipolar transistor with considering the change of thermal conductivity with temperature.The influence caused by the thermal conductivity can be equivalent to the increment of the local temperature surrounding the individual device. The junction temperature for each device can be efficiently calculated by the combination of the semianalytic temperature distribution function and the iteration of local temperature with high accuracy, providing a temperature distribution for a full chip. Applying this method to the InP frequency divider chip and the GaAs analog to digital converter chip, the computational results well agree with the results from the simulator COMSOL and the infrared thermal imager respectively. The proposed method can also be applied to thermal analysis in various kinds of semiconductor integrated circuits.
基金This work was supported by National Natural Science Foundation of China(No.U19B2028).
文摘A scanning and uniform array architecture with large spacing,low complexity and high scalability is presented for high integration massive array applications.It is constructed by offset phase center elements arranged in a uniform and regular way,but its spacing can be larger than that of traditional arrays.An ideal model of the offset phase center element is established and its far-field distribution is derived.To suppress grating lobes,the phase center of any element is designed to be movable without changing its physical position.Using genetic algorithm(GA),a new constraint condition limiting the number of phase center changes is proposed to solve the objective function of the minimum values of grating lobes(GLs)and side lobes(SLs).It is shown that the optimal results can be achieved by two changes of phase centers.A multimode circular patch is developed and designed,and characteristics of the offset phase center are analyzed and verified.A prototype array of 12×12 offset phase center elements is implemented based on multi-mode circular patches.Full wave simulation results of radiation patterns show that the level of grating lobes is suppressed at least 7dB with 1.12λ spacing,while the scanning angle is 20°.
基金the National Natural Science Foundation of China(Nos.12004353,11975214,11991071,11905202,12174350)Key Laboratory Foundation of The Sciences and Technology on Plasma Physics Laboratory(No.6142A04200103)Independent scientific research(No.JCKYS2021212011).
文摘Particle accelerators are indispensable tools in both science and industry.However,the size and cost of conventional RF accelerators limits the utility and scope of this technology.Recent research has shown that a dielectric laser accelerator(DLA)made of dielectric structures and driven at optical frequencies can generate particle beams with energies ranging from MeV to GeV at the tabletop level.To design DLA structures with a high acceleration gradient,we demonstrate topology optimization,which is a method used to optimize the material distribution in a specific area based on given load conditions,constraints,and performance indicators.To demonstrate the effectiveness of this approach,we propose two schemes and design several acceleration structures based on them.The optimization results demonstrate that the proposed method can be applied to structure optimization for on-chip integrated laser accelerators,producing manufacturable structures with significantly improved performance compared with previous size or shape optimization methods.These results provide new physical approaches to explore ultrafast dynamics in matter,with important implications for future laser particle accelerators based on photonic chips.
文摘底栏栅式渠首是新疆粗颗粒山溪性河流引水防沙枢纽的首选类型,但实践运用表明,当引水量超过30 m 3/s时,渠首冲沙有利、工程布置紧凑的优势逐渐丧失,后期运行管理效益大打折扣。为此在保留原有布置优势的情况下,以扩大底栏栅引水流量为目标,提出了“⊥”型廊道新结构及优化布置方案,新结构在原垂直水流方向“—”型廊道结构基础上增设了顺水流方向“|”型廊道(根据流量的大小可布置双排甚至多排“|”型廊道),并结合底栏栅水流动力方程及取水流量计算方法得到了“⊥”型廊道取水流量的计算方法。随后以新疆头屯河渠首为例,在保持原平面布置不变的情况下引入“⊥”型廊道新结构,其引水量可达48.96 m 3/s,提升了39.89%,工程造价降低了63.46%。“⊥”型廊道新结构及布置方案突破了传统底栏栅式渠首设计引水流量相对较小的限制,拓宽了底栏栅式渠首的适用范围,还提高了经济效益,可为此类工程提供新的工程方案。
