High mobility quasi two-dimensional electron gas(2DEG)found at the CaZrO_(3)/SrTiO_(3) nonpolar heterointerface is attractive and provides a platform for the development of functional devices and nanoelectronics.Here ...High mobility quasi two-dimensional electron gas(2DEG)found at the CaZrO_(3)/SrTiO_(3) nonpolar heterointerface is attractive and provides a platform for the development of functional devices and nanoelectronics.Here we report that the carrier density and mobility at low temperature can be tuned by gate voltage at the CaZrO_(3)/SrTiO_(3) interface.Furthermore,the magnitude of Rashba spin-orbit interaction can be modulated and increases with the gate voltage.Remarkably,the diffusion constant and the spin-orbit relaxation time can be strongly tuned by gate voltage.The diffusion constant increases by a factor of~19.98 and the relaxation time is reduced by a factor of over three orders of magnitude while the gate voltage is swept from-50 V to 100 V.These findings not only lay a foundation for further understanding the underlying mechanism of Rashba spin-orbit coupling,but also have great significance in developing various oxide functional devices.展开更多
The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation res...The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.展开更多
Stress voltages on time-dependent breakdown characteristics of GaN MIS-HEMTs during negative gate bias stress (with VGS < 0, VD = VS = 0) and off-state stress (VG < VTh, VDS > 0, VS = 0) are investigated. For...Stress voltages on time-dependent breakdown characteristics of GaN MIS-HEMTs during negative gate bias stress (with VGS < 0, VD = VS = 0) and off-state stress (VG < VTh, VDS > 0, VS = 0) are investigated. For negative bias stress, the breakdown time distribution (β) decreases with the increasing negative gate voltage, while β is larger for higher drain voltage at off-state stress. Two humps in the time-dependent gate leakage occurred under both breakdown conditions, which can be ascribed to the dielectric breakdown triggered earlier and followed by the GaN layer breakdown. Combining the electric distribution from simulation and long-term monitoring of electric parameter, the peak electric fields under the gate edges at source and drain sides are confirmed as the main formation locations for per-location paths during negative gate voltage stress and off-state stress, respectively.展开更多
In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the...In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing （PDA） times. The equivalent oxide thickness （EOT） decreases when the annealing time（s） change from 1 to 2. Furthermore, the characteristics of SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time（s） from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.展开更多
In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the...In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.展开更多
We propose a scheme for implementing conditional quantum phase gates for two four-state atoms trapped in a cavity. The two ground states of the atoms are coupled through two Raman processes induced by the cavity mode ...We propose a scheme for implementing conditional quantum phase gates for two four-state atoms trapped in a cavity. The two ground states of the atoms are coupled through two Raman processes induced by the cavity mode and two classical fields. Under certain conditions nonresonant Raman processes lead to two-atom coupling and can be used to produce conditional phase gates. The scheme is insensitive to cavity decay, thermal photons, and atomic spontaneous emission. The scheme does not require individual addressing of the atoms.展开更多
We propose a scheme for controllably implementing an N-qubit phase gate by one step within a ground-state subspace of N three-state atoms trapped in a cavity through a double Raman passage. We can extend our scheme to...We propose a scheme for controllably implementing an N-qubit phase gate by one step within a ground-state subspace of N three-state atoms trapped in a cavity through a double Raman passage. We can extend our scheme to the realisation of an arbitrary N-qubit phase gate by appropriately adjusting coupling strengths and detunings between atoms and external driving fields. The advantage of this one-step scheme is its robustness against decoherence.展开更多
The repetitive unclamped inductive switching(UIS)avalanche stress is conducted to investigate the degradation and breakdown behaviors of conventional shield gate trench MOSFET(C-SGT)and P-ring SGT MOSFETs(P-SGT).It is...The repetitive unclamped inductive switching(UIS)avalanche stress is conducted to investigate the degradation and breakdown behaviors of conventional shield gate trench MOSFET(C-SGT)and P-ring SGT MOSFETs(P-SGT).It is found that the static and dynamic parameters of both devices show different degrees of degradation.Combining experimental and simulation results,the hot holes trapped into the Si/SiO_(2) interface and the increase of crystal lattice temperature should be responsible for the degradation and breakdown behaviors.Moreover,under repetitive UIS avalanche stress,the reliability of P-SGT overcomes that of C-SGT,benefitting from the decreasing of the impact ionization rate at bottom of field oxide caused by the existence of P-ring.展开更多
The shallow trench isolation （STI） induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper we designed two types of devices to investigate this effect, and all lea...The shallow trench isolation （STI） induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage （Isub）, gate-induced-drain-leakage （/GIDL）, gate edge-direct-tunnelling leakage （IEDT） and band-to-band-tunnelling leakage （IBTBT） were analysed. For NMOS, Isub can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.展开更多
基金supported by the National Natural Science Foundation of China(Grants Nos.92065110,11974048,and 12074334)。
文摘High mobility quasi two-dimensional electron gas(2DEG)found at the CaZrO_(3)/SrTiO_(3) nonpolar heterointerface is attractive and provides a platform for the development of functional devices and nanoelectronics.Here we report that the carrier density and mobility at low temperature can be tuned by gate voltage at the CaZrO_(3)/SrTiO_(3) interface.Furthermore,the magnitude of Rashba spin-orbit interaction can be modulated and increases with the gate voltage.Remarkably,the diffusion constant and the spin-orbit relaxation time can be strongly tuned by gate voltage.The diffusion constant increases by a factor of~19.98 and the relaxation time is reduced by a factor of over three orders of magnitude while the gate voltage is swept from-50 V to 100 V.These findings not only lay a foundation for further understanding the underlying mechanism of Rashba spin-orbit coupling,but also have great significance in developing various oxide functional devices.
文摘The conduction mechanism of stress induced leakage current （SILC） through 2nm gate oxide is studied over a gate voltage range between 1.7V and stress voltage under constant voltage stress （CVS）. The simulation results show that the SILC is formed by trap-assisted tunnelling （TAT） process which is dominated by oxide traps induced by high field stresses. Their energy levels obtained by this work are approximately 1.9eV from the oxide conduction band, and the traps are believed to be the oxygen-related donor-like defects induced by high field stresses. The dependence of the trap density on stress time and oxide electric field is also investigated.
基金Project supported by the National Key Research and Development Program,China(Grant No.2017YFB0402800)the Key Research and Development Program of Guangdong Province,China(Grant Nos.2019B010128002 and 2020B010173001)+4 种基金the National Natural Science Foundation of China(Grant No.U1601210)the Natural Science Foundation of Guangdong Province,China(Grant No.2015A030312011)the Open Project of Key Laboratory of Microelectronic Devices and Integrated Technology(Grant No.202006)the Science and Technology Plan of Guangdong Province,China(Grant No.2017B010112002)the China Postdoctoral Science Foundation(Grant No.2019M663233).
文摘Stress voltages on time-dependent breakdown characteristics of GaN MIS-HEMTs during negative gate bias stress (with VGS < 0, VD = VS = 0) and off-state stress (VG < VTh, VDS > 0, VS = 0) are investigated. For negative bias stress, the breakdown time distribution (β) decreases with the increasing negative gate voltage, while β is larger for higher drain voltage at off-state stress. Two humps in the time-dependent gate leakage occurred under both breakdown conditions, which can be ascribed to the dielectric breakdown triggered earlier and followed by the GaN layer breakdown. Combining the electric distribution from simulation and long-term monitoring of electric parameter, the peak electric fields under the gate edges at source and drain sides are confirmed as the main formation locations for per-location paths during negative gate voltage stress and off-state stress, respectively.
基金supported by the National High Technology Research and Development Program of China(Grant No.2015AA016501)the National Natural Science Foundation of China(Grant No.61306129)
文摘In the process of high-k films fabrication, a novel multi deposition multi annealing （MDMA） technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing （PDA） times. The equivalent oxide thickness （EOT） decreases when the annealing time（s） change from 1 to 2. Furthermore, the characteristics of SILC （stress-induced leakage current） for an ultra-thin SiO2/HfO2 gate dielectric stack are studied systematically. The increase of the PDA time（s） from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes.
基金supported by the Research Program of the National University of Defense Technology(Grant No.JC 13-06-04)
文摘In this paper, the three-dimensional （3D） coupling effect is discussed for nanowire junctionless silicon-on-insulator （SOI） FinFETs. With fin width decreasing from 100 nm to 7 nm, the electric field induced by the lateral gates increases and therefore the influence of back gate on the threshold voltage weakens. For a narrow and tall fin, the lateral gates mainly control the channel and therefore the effect of back gate decreases. A simple two-dimensional （2D） potential model is proposed for the subthreshold region of junctionless SO1 FinFET. TCAD simulations validate our model. It can be used to extract the threshold voltage and doping concentration. In addition, the tuning of back gate on the threshold voltage can be predicted.
基金supported by the National Natural Science Foundation of China (Grant No 10674025)the Doctoral Foundation of the Ministry of Education of China (Grant No 20070386002)
文摘We propose a scheme for implementing conditional quantum phase gates for two four-state atoms trapped in a cavity. The two ground states of the atoms are coupled through two Raman processes induced by the cavity mode and two classical fields. Under certain conditions nonresonant Raman processes lead to two-atom coupling and can be used to produce conditional phase gates. The scheme is insensitive to cavity decay, thermal photons, and atomic spontaneous emission. The scheme does not require individual addressing of the atoms.
基金Project supported by the National Natural Science Foundation of China (Grant Nos. 60578055 and 60978009)the National Basic Research Program of China(Grant Nos. 2007CB925204 and 2009CB929604)
文摘We propose a scheme for controllably implementing an N-qubit phase gate by one step within a ground-state subspace of N three-state atoms trapped in a cavity through a double Raman passage. We can extend our scheme to the realisation of an arbitrary N-qubit phase gate by appropriately adjusting coupling strengths and detunings between atoms and external driving fields. The advantage of this one-step scheme is its robustness against decoherence.
基金Project supported by the National Natural Science Foundation of China(Grant No.61504049)Jiangsu Province Postdoctoral Science Foundation(Grant No.2018K057B)the Fundamental Research Funds for the Central Universities,China(Grant No.JUSRP51510).
文摘The repetitive unclamped inductive switching(UIS)avalanche stress is conducted to investigate the degradation and breakdown behaviors of conventional shield gate trench MOSFET(C-SGT)and P-ring SGT MOSFETs(P-SGT).It is found that the static and dynamic parameters of both devices show different degrees of degradation.Combining experimental and simulation results,the hot holes trapped into the Si/SiO_(2) interface and the increase of crystal lattice temperature should be responsible for the degradation and breakdown behaviors.Moreover,under repetitive UIS avalanche stress,the reliability of P-SGT overcomes that of C-SGT,benefitting from the decreasing of the impact ionization rate at bottom of field oxide caused by the existence of P-ring.
文摘The shallow trench isolation （STI） induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage （Isub）, gate-induced-drain-leakage （/GIDL）, gate edge-direct-tunnelling leakage （IEDT） and band-to-band-tunnelling leakage （IBTBT） were analysed. For NMOS, Isub can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.
