期刊文献+
共找到2篇文章
< 1 >
每页显示 20 50 100
Numerical Simulation of Coal Floor Fault Activation Influenced by Mining 被引量:24
1
作者 WANG Lian-guo MIAO Xie-xing 《Journal of China University of Mining and Technology》 EI 2006年第4期385-388,共4页
By means of the numerical simulation software ANSYS, the activation regularity of coal floor faults caused by mining is simulated. The results indicate that the variation in horizontal, vertical and shear stresses, as... By means of the numerical simulation software ANSYS, the activation regularity of coal floor faults caused by mining is simulated. The results indicate that the variation in horizontal, vertical and shear stresses, as well as the horizontal and vertical displacements in the upper and the lower fault blocks at the workface are almost identical. Influ- enced by mining of the floor rock, there are stress releasing and stress rising areas at the upper part and at the footwall of the fault. The distribution of stress is influenced by the fault so that the stress isolines are staggered by the fault face and the stress is focused on the rock seam around the two ends of the fault. But the influence in fault activation on the upper or the lower fault blocks of the workface is markedly different. When the workface is on the footwall of the fault, there is a horizontal tension stress area on the upper part of the fault; when the workface is on the upper part of the fault, it has a horizontal compressive stress area on the lower fault block. When the workface is at the lower fault block, the maximum vertical displacement is 5 times larger then when the workface is on the upper fault block, which greatly in- creases the chance of a fatal inrush of water from the coal floor. 展开更多
关键词 MINING fault activation: simulation
在线阅读 下载PDF
基于FCM flow的小规模数字电路芯片测试
2
作者 崔震 周立阳 +2 位作者 刘萌 赵禹 王学德 《电子技术应用》 2023年第8期24-29,共6页
随着芯片工艺的不断演进,数字芯片的规模急剧增加,测试成本进一步增加。目前先进的DFT技术已应用于大规模SoC芯片的测试,包括扫描路径设计、JTAG、ATPG(自动测试向量生成)等。但对于一些小规模集成电路,插入扫描链等测试电路会增加芯片... 随着芯片工艺的不断演进,数字芯片的规模急剧增加,测试成本进一步增加。目前先进的DFT技术已应用于大规模SoC芯片的测试,包括扫描路径设计、JTAG、ATPG(自动测试向量生成)等。但对于一些小规模集成电路,插入扫描链等测试电路会增加芯片面积并增加额外的功耗。对于这种芯片,功能case生成的pattern可用于检测制造缺陷和故障。因此,需要一些方法来验证覆盖率是否达到了目标。Verisium manager工具依靠Xcelium的故障仿真引擎和Jasper功能安全验证应用程序(FSV)可以解决这个问题。它为ATE(自动测试设备)pattern的覆盖率分析提供了一个新的思路。 展开更多
关键词 DFT 覆盖率 Verisium manager Xcelium fault simulator JASPER
在线阅读 下载PDF
上一页 1 下一页 到第
使用帮助 返回顶部