为设计高效稳定的演化算法,将方程求根的不动点迭代思想引入到优化领域,通过将演化算法的寻优过程看作为在迭代框架下方程不动点的逐步显示化过程,设计出一种基于数学模型的演化新算法,即不动点演化算法(fixed point evolution algorith...为设计高效稳定的演化算法,将方程求根的不动点迭代思想引入到优化领域,通过将演化算法的寻优过程看作为在迭代框架下方程不动点的逐步显示化过程,设计出一种基于数学模型的演化新算法,即不动点演化算法(fixed point evolution algorithm,FPEA).该算法的繁殖算子是由Aitken加速的不动点迭代模型导出的二次多项式,其整体框架继承传统演化算法(如差分演化算法)基于种群的迭代模式.试验结果表明:在基准函数集CEC2014、CEC2019上,本文算法的最优值平均排名在所有比较算法中排名第1;在4个工程约束设计问题上,FPEA与CSA、GPE等多个算法相比,能以较少的计算开销获得最高的求解精度.展开更多
A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, (i.e.) ...A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, (i.e.) let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91 6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.展开更多
文摘为设计高效稳定的演化算法,将方程求根的不动点迭代思想引入到优化领域,通过将演化算法的寻优过程看作为在迭代框架下方程不动点的逐步显示化过程,设计出一种基于数学模型的演化新算法,即不动点演化算法(fixed point evolution algorithm,FPEA).该算法的繁殖算子是由Aitken加速的不动点迭代模型导出的二次多项式,其整体框架继承传统演化算法(如差分演化算法)基于种群的迭代模式.试验结果表明:在基准函数集CEC2014、CEC2019上,本文算法的最优值平均排名在所有比较算法中排名第1;在4个工程约束设计问题上,FPEA与CSA、GPE等多个算法相比,能以较少的计算开销获得最高的求解精度.
文摘A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, (i.e.) let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91 6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.
