In order to improve the performance of arithmetic very large-scale integration （VLSI） sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode （MVCM） by using dynamic...In order to improve the performance of arithmetic very large-scale integration （VLSI） sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode （MVCM） by using dynamic source-coupled logic （SCL）. Its key components, the comparator and the output generator are both based on differential-pair circuit （DPC）, and the latter is constructed by using the structure of DPC trees. The pre-charge evaluates logic style makes a steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source- coupled logic and differential-pair circuit makes it lower power consumption and more compact. The performance is evaluated by HSPICE simulation with 0.18 ~m CMOS technology. The power dissipa- tion, transistor numbers and delay are superior to corresponding binary CMOS implementation. Mul- tiple-valued logic will be the potential solution for the high performance arithmetic VLSI system in the future.展开更多
In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low...In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.展开更多
为克服传统静态CMOS电路在高频工作时的缺陷,引入了MOS电流模逻辑(MOS Current Mode Logic,MCML)电路.MCML电路是一种差分对称结构逻辑电路,与传统的CMOS电路比较,在高频段工作时功耗相对较低,具有典型的高速低功耗特性.在对MCML电路的...为克服传统静态CMOS电路在高频工作时的缺陷,引入了MOS电流模逻辑(MOS Current Mode Logic,MCML)电路.MCML电路是一种差分对称结构逻辑电路,与传统的CMOS电路比较,在高频段工作时功耗相对较低,具有典型的高速低功耗特性.在对MCML电路的开关条件以及具有不同输入端的MCML逻辑门电路进行分析后,提出了实现MCML加法器的两种电路结构,并给出了不同结构的应用条件.仿真结果验证了电路结构设计的有效性.展开更多
基金Supported by Beijing Institute of Technology Science Foundation(3050012211106)
文摘In order to improve the performance of arithmetic very large-scale integration （VLSI） sys- tem, a novel structure of quaternary logic gates is proposed based on multiple-valued current mode （MVCM） by using dynamic source-coupled logic （SCL）. Its key components, the comparator and the output generator are both based on differential-pair circuit （DPC）, and the latter is constructed by using the structure of DPC trees. The pre-charge evaluates logic style makes a steady current flow cut off, thereby greatly saving the power dissipation. The combination of multiple-valued source- coupled logic and differential-pair circuit makes it lower power consumption and more compact. The performance is evaluated by HSPICE simulation with 0.18 ~m CMOS technology. The power dissipa- tion, transistor numbers and delay are superior to corresponding binary CMOS implementation. Mul- tiple-valued logic will be the potential solution for the high performance arithmetic VLSI system in the future.
基金supported by the Fundamental Research Funds for the Central Universities under Grant No.2009JBM001
文摘In this paper, a phase interpolator clock and data recovery （CDR） with low-voltage current mode logic （CML） latched, buffers, and muxes is presented. Because of using the CML circuits, the CDR can operate in a low supply voltage. And the original swing of the differential inputs and outputs is less than that of the CMOS logic. The power supply voltage is 1.2 V, and the static current consumption is about 20 mA. In this phase interpolator CDR, the charge pump and loop filter are replaced by a digital filter. And this structure offers the benefits of increased system stability and faster acquisition.
文摘光纤通信在大数据时代得到广泛的应用,其速度快、带宽大、可靠性高的特点满足了对长距离、大容量信息传输的要求。前置放大器作为光接收器的前端,其性能高低直接影响到整个光接收系统的工作性能。基于SMIC 0.13μm CMOS工艺,设计完成了一款5 Gbps光接收前置放大器。首先,整体差分式结构可以消除共模噪声的干扰,降低放大器的等效输入噪声。其次,采用共源共栅的输入结构具有低输入阻抗的特点,能有效抑制光电管大电容带来的不利影响。最后,输出级采用电流模逻辑结构,解决了输出增益与带宽之间的矛盾。仿真结果表明,放大器增益达到62 d BΩ,带宽4.7 GHz;等效输入噪声30.1 p A/Hz,眼图迹线清晰,张开度较大,能够满足5 Gbps平衡光探测器通信要求。
文摘为克服传统静态CMOS电路在高频工作时的缺陷,引入了MOS电流模逻辑(MOS Current Mode Logic,MCML)电路.MCML电路是一种差分对称结构逻辑电路,与传统的CMOS电路比较,在高频段工作时功耗相对较低,具有典型的高速低功耗特性.在对MCML电路的开关条件以及具有不同输入端的MCML逻辑门电路进行分析后,提出了实现MCML加法器的两种电路结构,并给出了不同结构的应用条件.仿真结果验证了电路结构设计的有效性.
