With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper first...With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper firstly explains the benefits and design implications of the hybrid beamforming structure in terms of the mmWave spectrum characteristics,energy efficiency,data rate,communication capacity,coverage and implementation technology choices.Then after reviewing the techniques to improve the power amplifier(PA)output power and efficiency,the design considerations and test results of 60 GHz and 90 GHz mmWave PAs in bulk complementary metal oxide semiconductor(CMOS)process are shown.展开更多
A 60 GHz phased array system for mm wave frequency in 5G is introduced and a 5 bit digitally controlled phase shifter in 40 nm CMOS technology is presented.In a phased array system,the signal to noise ratio(SNR)of the...A 60 GHz phased array system for mm wave frequency in 5G is introduced and a 5 bit digitally controlled phase shifter in 40 nm CMOS technology is presented.In a phased array system,the signal to noise ratio(SNR)of the receiver is improved with the beaming forming function.Therefore,the communication data rate and distance are improved accordingly.The phase shifter is the key component for achieving the beam forming function,and its resolution and power consumption are also very critical.In the second half of this paper,an analysis of phase shifter is introduced,and a 60 GHz 5 bit digitally controlled phase shifter in 40 nm complementary metal oxide semiconductor(CMOS)technology is presented.In this presented phase shifter,a hybrid structure is implemented for its advantage on lower phase deviation while keeping comparable loss.Meanwhile,this digitally controlled phase shifter is much more compact than other works.For all 32 states,the minimum phase error is 1.5°,and the maximum phase error is 6.8°.The measured insertion loss is-20.9±1 dB including pad loss at 60 GHz and the return loss is more than 10 dB over 57-64 GHz.The total chip size is 0.24 mm^2 with 0 mW DC power consumption.展开更多
We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a...We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.展开更多
The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and ...The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.展开更多
基金supported by the National Natural Science Foundations of China (Nos. 61306030, 61674037)the National Key R&D Program of China (Nos.2016YFC0800400, 2018YFE0205900)the National Science and Technology Major Project (No. 2018ZX03001008)
文摘With targets of cost reduction per bit and high energy efficiency,5G and beyond call for innovation in the mmWave transmitter architecture and the power amplifier(PA)circuit.To illustrate these points,this paper firstly explains the benefits and design implications of the hybrid beamforming structure in terms of the mmWave spectrum characteristics,energy efficiency,data rate,communication capacity,coverage and implementation technology choices.Then after reviewing the techniques to improve the power amplifier(PA)output power and efficiency,the design considerations and test results of 60 GHz and 90 GHz mmWave PAs in bulk complementary metal oxide semiconductor(CMOS)process are shown.
基金supported by the National Science Foundation of China (No. 61828401)
文摘A 60 GHz phased array system for mm wave frequency in 5G is introduced and a 5 bit digitally controlled phase shifter in 40 nm CMOS technology is presented.In a phased array system,the signal to noise ratio(SNR)of the receiver is improved with the beaming forming function.Therefore,the communication data rate and distance are improved accordingly.The phase shifter is the key component for achieving the beam forming function,and its resolution and power consumption are also very critical.In the second half of this paper,an analysis of phase shifter is introduced,and a 60 GHz 5 bit digitally controlled phase shifter in 40 nm complementary metal oxide semiconductor(CMOS)technology is presented.In this presented phase shifter,a hybrid structure is implemented for its advantage on lower phase deviation while keeping comparable loss.Meanwhile,this digitally controlled phase shifter is much more compact than other works.For all 32 states,the minimum phase error is 1.5°,and the maximum phase error is 6.8°.The measured insertion loss is-20.9±1 dB including pad loss at 60 GHz and the return loss is more than 10 dB over 57-64 GHz.The total chip size is 0.24 mm^2 with 0 mW DC power consumption.
基金supported by the National Natural Science Foundation of China(Grant No.61307128)the National Basic Research Program of China(GrantNo.2010CB327505)+1 种基金the Specialized Research Found for the Doctoral Program of Higher Education of China(Grant No.20131101120027)the Basic Research Foundation of Beijing Institute of Technology of China(Grant No.20120542015)
文摘We propose a novel hybrid phase-locked loop （PLL） architecture for overcoming the trade-off between fast locking time and low spur. To reduce the settling time and meanwhile suppress the reference spurs, we employ a wide-band single-path PLL and a narrow-band dual-path PLL in a transient state and a steady state, respectively, by changing the loop bandwidth according to the gain of voltage controlled oscillator （VCO） and the resister of the loop filter. The hybrid PLL is implemented in a 0.18-μm complementary metal oxide semiconductor （CMOS） process with a total die area of 1.4×0.46 mm2. The measured results exhibit a reference spur level of lower than -73 dB with a reference frequency of 10 MHz and a settling time of 20 μs with 40 MHz frequency jump at 2 GHz. The total power consumption of the hybrid PLL is less than 27 mW with a supply voltage of 1.8 V.
文摘The compact full custom layout design of a 16 kbit mask-programmable complementary metal oxide semiconductor (CMOS) read only memory (ROM) with low power dissipation is introduced. By optimizing storage cell size and peripheral circuit structure, the ROM has a small area of 0.050 mm2 with a power-delay product of 0.011 pJ/bit at +1.8 V. The high packing density and the excellent power-delay product have been achieved by using SMIC 0.18 μm 1P6M CMOS technology. A novel and simple sense amplifier/driver structure is presented which restores the signal full swing efficiently and reduces the signal rising time by 2.4 ns, as well as the memory access time. The ROM has a fast access time of 8.6 ns. As a consequence, the layout design not only can be embedded into microprocessor system as its program memory, but also can be fabricated individually as ROM ASIC.
