InGaAs high electron mobility transistors （HEMTs） on InP substrate with very good device performance have been grown by mental organic chemical vapor deposition （MOCVD）. Room temperature Hall mobilities of the 2-D...InGaAs high electron mobility transistors （HEMTs） on InP substrate with very good device performance have been grown by mental organic chemical vapor deposition （MOCVD）. Room temperature Hall mobilities of the 2-DEG are measured to be over 8 700 cm^2/V-s with sheet carrier densities larger than 4.6× 10^12 cm^ 2. Transistors with 1.0 μm gate length exhibits transconductance up to 842 mS/ram. Excellent depletion-mode operation, with a threshold voltage of-0.3 V and IDss of 673 mA/mm, is realized. The non-alloyed ohmic contact special resistance is as low as 1.66×10^-8 Ω/cm^2, which is so far the lowest ohmic contact special resistance. The unity current gain cut off frequency （fT） and the maximum oscillation frequency （fmax） are 42.7 and 61.3 GHz, respectively. These results are very encouraging toward manufacturing InP-based HEMT by MOCVD.展开更多
Organic thin film transistors (OTFTs) have attracted much attention in low-cost, large area wearable electronics in the recent years[1-3]. The electrical stability performance of these devices under stretching is crit...Organic thin film transistors (OTFTs) have attracted much attention in low-cost, large area wearable electronics in the recent years[1-3]. The electrical stability performance of these devices under stretching is critical for applications in wearable electronics[4].Organic semiconductors have been widely used for wearable electronics due to their electrical properties of intrinsic materials and the mechanical properties of organic compounds, which can be deposited with low-cost solution processed techniques.展开更多
In this paper,the small-signal modeling of the Indium Phosphide High Electron Mobility Transistor(InP HEMT)based on the Transformer neural network model is investigated.The AC S-parameters of the HEMT device are train...In this paper,the small-signal modeling of the Indium Phosphide High Electron Mobility Transistor(InP HEMT)based on the Transformer neural network model is investigated.The AC S-parameters of the HEMT device are trained and validated using the Transformer model.In the proposed model,the eight-layer transformer encoders are connected in series and the encoder layer of each Transformer consists of the multi-head attention layer and the feed-forward neural network layer.The experimental results show that the measured and modeled S-parameters of the HEMT device match well in the frequency range of 0.5-40 GHz,with the errors versus frequency less than 1%.Compared with other models,good accuracy can be achieved to verify the effectiveness of the proposed model.展开更多
In this work,we investigate the impact of the whole small recess offset on DC and RF characteristics of InP high electron mobility transistors(HEMTs).L_(g)=80 nm HEMTs are fabricated with a double-recessed gate proces...In this work,we investigate the impact of the whole small recess offset on DC and RF characteristics of InP high electron mobility transistors(HEMTs).L_(g)=80 nm HEMTs are fabricated with a double-recessed gate process.We focus on their DC and RF responses,including the maximum transconductance(g_(m_max)),ON-resistance(R_(ON)),current-gain cutoff frequency(f_(T)),and maximum oscillation frequency(f_(max)).The devices have almost same RON.The g_(m_max) improves as the whole small recess moves toward the source.However,a small gate to source capacitance(C_(gs))and a small drain output conductance(g_(ds))lead to the largest f_(T),although the whole small gate recess moves toward the drain leads to the smaller g_(m_max).According to the small-signal modeling,the device with the whole small recess toward drain exhibits an excellent RF characteristics,such as f_(T)=372 GHz and f_(max)=394 GHz.This result is achieved by paying attention to adjust resistive and capacitive parasitics,which play a key role in high-frequency response.展开更多
增强型氮化镓(GaN)基高电子迁移率晶体管(high electron mobility transistor,HEMT)是高频高功率器件与开关器件领域的研究热点,P-GaN栅技术因具备制备工艺简单、可控且工艺重复性好等优势而成为目前最常用且唯一实现商用的GaN基增强型...增强型氮化镓(GaN)基高电子迁移率晶体管(high electron mobility transistor,HEMT)是高频高功率器件与开关器件领域的研究热点,P-GaN栅技术因具备制备工艺简单、可控且工艺重复性好等优势而成为目前最常用且唯一实现商用的GaN基增强型器件制备方法。首先,概述了当前制约P-GaN栅结构GaN基HEMT器件发展的首要问题,从器件结构与器件制备工艺这2个角度,综述了其性能优化举措方面的最新研究进展。然后,通过对研究进展的分析,总结了当前研究工作面临的挑战以及解决方法。最后,对未来的发展前景、发展方向进行了展望。展开更多
Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high perfor...Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.展开更多
The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents...The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.展开更多
A novel grain boundary(GB) model characterized with different angles and positions in the nanowire was set up.By means of device simulator,the effects of grain boundary angle and location on the electrical performance...A novel grain boundary(GB) model characterized with different angles and positions in the nanowire was set up.By means of device simulator,the effects of grain boundary angle and location on the electrical performance of ZnO nanowire FET(Nanowire Field-Effect Transistor) with a wrap-around gate configuration,were explored.With the increase of the grain boundary angle,the electrical performance degrades gradually.When a grain boundary with a smaller angle,such as 5° GB,is located close to the source or drain electrode,the grain boundary is partially depleted by an electric field peak,which leads to the decrease of electron concentration and the degradation of transistor characteristics.When the 90° GB is located at the center of the nanowire,the action of the electric field is balanced out,so the electrical performance of transistor is better than that of the 90° GB located at the other positions.展开更多
The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First...The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.展开更多
As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the mo...As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.展开更多
基金Project(Z132012A001)supported by the Technical Basis Research Program in Science and Industry Bureau of ChinaProject(61201028,60876009)supported by the National Natural Science Foundation of China
文摘InGaAs high electron mobility transistors （HEMTs） on InP substrate with very good device performance have been grown by mental organic chemical vapor deposition （MOCVD）. Room temperature Hall mobilities of the 2-DEG are measured to be over 8 700 cm^2/V-s with sheet carrier densities larger than 4.6× 10^12 cm^ 2. Transistors with 1.0 μm gate length exhibits transconductance up to 842 mS/ram. Excellent depletion-mode operation, with a threshold voltage of-0.3 V and IDss of 673 mA/mm, is realized. The non-alloyed ohmic contact special resistance is as low as 1.66×10^-8 Ω/cm^2, which is so far the lowest ohmic contact special resistance. The unity current gain cut off frequency （fT） and the maximum oscillation frequency （fmax） are 42.7 and 61.3 GHz, respectively. These results are very encouraging toward manufacturing InP-based HEMT by MOCVD.
文摘Organic thin film transistors (OTFTs) have attracted much attention in low-cost, large area wearable electronics in the recent years[1-3]. The electrical stability performance of these devices under stretching is critical for applications in wearable electronics[4].Organic semiconductors have been widely used for wearable electronics due to their electrical properties of intrinsic materials and the mechanical properties of organic compounds, which can be deposited with low-cost solution processed techniques.
基金Supported by the National Natural Science Foundation of China(62201293,62034003)the Open-Foundation of State Key Laboratory of Millimeter-Waves(K202313)the Jiangsu Province Youth Science and Technology Talent Support Project(JSTJ-2024-040)。
文摘In this paper,the small-signal modeling of the Indium Phosphide High Electron Mobility Transistor(InP HEMT)based on the Transformer neural network model is investigated.The AC S-parameters of the HEMT device are trained and validated using the Transformer model.In the proposed model,the eight-layer transformer encoders are connected in series and the encoder layer of each Transformer consists of the multi-head attention layer and the feed-forward neural network layer.The experimental results show that the measured and modeled S-parameters of the HEMT device match well in the frequency range of 0.5-40 GHz,with the errors versus frequency less than 1%.Compared with other models,good accuracy can be achieved to verify the effectiveness of the proposed model.
基金Supported by the Terahertz Multi User RF Transceiver System Development Project(Z211100004421012).
文摘In this work,we investigate the impact of the whole small recess offset on DC and RF characteristics of InP high electron mobility transistors(HEMTs).L_(g)=80 nm HEMTs are fabricated with a double-recessed gate process.We focus on their DC and RF responses,including the maximum transconductance(g_(m_max)),ON-resistance(R_(ON)),current-gain cutoff frequency(f_(T)),and maximum oscillation frequency(f_(max)).The devices have almost same RON.The g_(m_max) improves as the whole small recess moves toward the source.However,a small gate to source capacitance(C_(gs))and a small drain output conductance(g_(ds))lead to the largest f_(T),although the whole small gate recess moves toward the drain leads to the smaller g_(m_max).According to the small-signal modeling,the device with the whole small recess toward drain exhibits an excellent RF characteristics,such as f_(T)=372 GHz and f_(max)=394 GHz.This result is achieved by paying attention to adjust resistive and capacitive parasitics,which play a key role in high-frequency response.
文摘增强型氮化镓(GaN)基高电子迁移率晶体管(high electron mobility transistor,HEMT)是高频高功率器件与开关器件领域的研究热点,P-GaN栅技术因具备制备工艺简单、可控且工艺重复性好等优势而成为目前最常用且唯一实现商用的GaN基增强型器件制备方法。首先,概述了当前制约P-GaN栅结构GaN基HEMT器件发展的首要问题,从器件结构与器件制备工艺这2个角度,综述了其性能优化举措方面的最新研究进展。然后,通过对研究进展的分析,总结了当前研究工作面临的挑战以及解决方法。最后,对未来的发展前景、发展方向进行了展望。
文摘Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.
基金Projects(61574109,61204092)supported by the National Natural Science Foundation of China
文摘The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.
基金Project(60876022) supported by the National Natural Science Foundation of ChinaProject(50925727) supported by the National Natural Science Funds for Distinguished Young Scholars of China
文摘A novel grain boundary(GB) model characterized with different angles and positions in the nanowire was set up.By means of device simulator,the effects of grain boundary angle and location on the electrical performance of ZnO nanowire FET(Nanowire Field-Effect Transistor) with a wrap-around gate configuration,were explored.With the increase of the grain boundary angle,the electrical performance degrades gradually.When a grain boundary with a smaller angle,such as 5° GB,is located close to the source or drain electrode,the grain boundary is partially depleted by an electric field peak,which leads to the decrease of electron concentration and the degradation of transistor characteristics.When the 90° GB is located at the center of the nanowire,the action of the electric field is balanced out,so the electrical performance of transistor is better than that of the 90° GB located at the other positions.
基金Project(P140c090303110c0904)supported by NLAIC Research Fund,ChinaProject(JY0300122503)supported by the Research Fund for the Doctoral Program of Higher Education of China+1 种基金Projects(K5051225014,K5051225004)supported by the Fundamental Research Funds for the Central Universities,ChinaProject(2010JQ8008)supported by the Natural Science Basic Research Plan in Shaanxi Province of China
文摘The tunnel field-effect transistor(TFET) is a potential candidate for the post-CMOS era.As one of the most important electrical parameters of a device,double gate TFET(DG-TFET) gate threshold voltage was studied.First,a numerical simulation study of transfer characteristic and gate threshold voltage in DG-TFET was reported.Then,a simple analytical model for DG-TFET gate threshold voltage VTG was built by solving quasi-two-dimensional Poisson equation in Si film.The model as a function of the drain voltage,the Si layer thickness,the gate length and the gate dielectric was discussed.It is shown that the proposed model is consistent with the simulation results.This model should be useful for further investigation of performance of circuits containing TFETs.
基金Project(61074051)supported by the National Natural Science Foundation of ChinaProject(10C0709)supported by the Scientific Research Fund of Education Department of Hunan Province,ChinaProject(2011GK3058)supported by the Science and Technology Plan of Hunan Province,China
文摘As dimensions of the metal-oxide-semiconductor field-effect transistor (MOSFET) are scaling down and the thickness of gate oxide is decreased,the gate leakage becomes more and more prominent and has been one of the most important limiting factors to MOSFET and circuits lifetime.Based on reliability theory and experiments,the direct tunneling current in lightly-doped drain (LDD) NMOSFET with 1.4 nm gate oxide fabricated by 90 nm complementary metal oxide semiconductor (CMOS) process was studied in depth.High-precision semiconductor parameter analyzer was used to conduct the tests.Law of variation of the direct tunneling (DT) current with channel length,channel width,measuring voltage,drain bias and reverse substrate bias was revealed.The results show that the change of the DT current obeys index law;there is a linear relationship between gate current and channel dimension;drain bias and substrate bias can reduce the gate current.
