针对三维片上网络(3D No C)中硅通孔(TSV)的特殊结构,提出了一种3D No C延迟上界优化方法,通过全局均衡硅通孔负载,降低全局业务流的延迟上界.建立3D No C的网格通信模型,搜索网络中所有业务流的可行路径,提出一种基于度的冲突矩阵,求...针对三维片上网络(3D No C)中硅通孔(TSV)的特殊结构,提出了一种3D No C延迟上界优化方法,通过全局均衡硅通孔负载,降低全局业务流的延迟上界.建立3D No C的网格通信模型,搜索网络中所有业务流的可行路径,提出一种基于度的冲突矩阵,求出目标子流路径的TSV冲突系数,按照路径中TSV冲突系数的大小把目标流流量分配到部分最优路径上.实验结果表明,基于度的冲突矩阵可以有效减少存储空间,将存储复杂度从O(n2)降低到O(n),并且可以清晰直观地表现出业务流在网络中的冲突情况.采用硅通孔负载全局均衡的3D No C延迟上界优化方法,目标业务流的延迟上界得到了显著优化,最大的优化效果可将延迟上界降低58.9%.展开更多
A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol ...A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.展开更多
三维片上网络(three-dimensional network on chip,3D No C)是在三维集成电路(three-dimensional integrated circuit,3D IC)、片上系统(system on chip,So C)和二维片上网络(two-dimensional network on chip,2D No C)的基础上发展起来...三维片上网络(three-dimensional network on chip,3D No C)是在三维集成电路(three-dimensional integrated circuit,3D IC)、片上系统(system on chip,So C)和二维片上网络(two-dimensional network on chip,2D No C)的基础上发展起来的,主要解决高集成度芯片通信瓶颈等问题,已引起国内外学术界和产业界的高度重视。3D No C拓扑结构体现了通信节点在芯片中的布局与连接,对三维芯片性能起决定性作用。简介了2D No C、2D No C到3D No C的演变、3D No C的优点与存在的问题以及3D No C解决的关键技术问题,分析了3D No C总体发展状况。三维拓扑结构是3D No C设计中的关键问题之一,重点研究了3D No C拓扑结构的分类方法,从通信角度将3D No C拓扑结构分成9大类,分类论述了3D No C拓扑结构,并分析比较了现有63种拓扑结构各自的特点,最后指出了3D No C拓扑结构的未来研究方向。展开更多
三维片上网络(3D No C)中IP核的测试问题日趋突出,测试规划是提高测试效率的有效方法。基于重用No C作为测试存取机制的并行测试方法,针对IP核测试数据传输带宽与TAM带宽不匹配的问题,提出带分复用方法,对有限带宽的TAM进行动态细分,将...三维片上网络(3D No C)中IP核的测试问题日趋突出,测试规划是提高测试效率的有效方法。基于重用No C作为测试存取机制的并行测试方法,针对IP核测试数据传输带宽与TAM带宽不匹配的问题,提出带分复用方法,对有限带宽的TAM进行动态细分,将多核的测试数据共享同一物理TAM实施并行传输,并结合3D No C结构设计二维编码,建立带宽分配和测试顺序模型,采用多种群遗传模拟退火算法,在总功耗、层功耗双重约束下对IP核的带宽分配和测试顺序进行双重优化,提高并行测试效率以获得最短测试时间。算法中针对测试顺序优化设计移位互换杂交策略,并运用精英配对方法加快种群寻优速度,设计求精操作进一步优化测试时间,通过比较、淘汰、替换机制加强种群间交流,增加种群多样性,避免算法陷入局部最优。以ITC'02标准电路作为测试对象,实验结果表明,该方法通过提高带宽利用率,提升了并行测试效率,降低了资源占用,有效地缩短了测试时间。展开更多
文摘针对三维片上网络(3D No C)中硅通孔(TSV)的特殊结构,提出了一种3D No C延迟上界优化方法,通过全局均衡硅通孔负载,降低全局业务流的延迟上界.建立3D No C的网格通信模型,搜索网络中所有业务流的可行路径,提出一种基于度的冲突矩阵,求出目标子流路径的TSV冲突系数,按照路径中TSV冲突系数的大小把目标流流量分配到部分最优路径上.实验结果表明,基于度的冲突矩阵可以有效减少存储空间,将存储复杂度从O(n2)降低到O(n),并且可以清晰直观地表现出业务流在网络中的冲突情况.采用硅通孔负载全局均衡的3D No C延迟上界优化方法,目标业务流的延迟上界得到了显著优化,最大的优化效果可将延迟上界降低58.9%.
基金supported by the High Technology Research and Development Program of Fujian Province(2010HZ0004-1,2009HZ0003-1)
文摘A dual-channel access mechanism to overcome the drawback of traditional single-channel access mechanism for network-on-chip （NoC） is proposed. In traditional single-channel access mechanism, every Internet protocol （IP） has only one chan- nel to access the on-chip network. When the network is relatively idle, the injection rate is too small to make good use of the network resource. When the network is relatively busy, the ejection rate is so small that the packets in the network cannot leave immediately, and thus the probability of congestion is increased. In the dual-channel access mechanism, the injection rate of IP and the ejection rate of the network are increased by using two optional channels in network interface （NI） and local port of routers. Therefore, the communication performance is improved. Experimental results show that compared with traditional single-channel access mechanism, the proposed scheme greatly increases the throughput and cuts down the average latency with reasonable area increase.
文摘三维片上网络(three-dimensional network on chip,3D No C)是在三维集成电路(three-dimensional integrated circuit,3D IC)、片上系统(system on chip,So C)和二维片上网络(two-dimensional network on chip,2D No C)的基础上发展起来的,主要解决高集成度芯片通信瓶颈等问题,已引起国内外学术界和产业界的高度重视。3D No C拓扑结构体现了通信节点在芯片中的布局与连接,对三维芯片性能起决定性作用。简介了2D No C、2D No C到3D No C的演变、3D No C的优点与存在的问题以及3D No C解决的关键技术问题,分析了3D No C总体发展状况。三维拓扑结构是3D No C设计中的关键问题之一,重点研究了3D No C拓扑结构的分类方法,从通信角度将3D No C拓扑结构分成9大类,分类论述了3D No C拓扑结构,并分析比较了现有63种拓扑结构各自的特点,最后指出了3D No C拓扑结构的未来研究方向。
文摘三维片上网络(3D No C)中IP核的测试问题日趋突出,测试规划是提高测试效率的有效方法。基于重用No C作为测试存取机制的并行测试方法,针对IP核测试数据传输带宽与TAM带宽不匹配的问题,提出带分复用方法,对有限带宽的TAM进行动态细分,将多核的测试数据共享同一物理TAM实施并行传输,并结合3D No C结构设计二维编码,建立带宽分配和测试顺序模型,采用多种群遗传模拟退火算法,在总功耗、层功耗双重约束下对IP核的带宽分配和测试顺序进行双重优化,提高并行测试效率以获得最短测试时间。算法中针对测试顺序优化设计移位互换杂交策略,并运用精英配对方法加快种群寻优速度,设计求精操作进一步优化测试时间,通过比较、淘汰、替换机制加强种群间交流,增加种群多样性,避免算法陷入局部最优。以ITC'02标准电路作为测试对象,实验结果表明,该方法通过提高带宽利用率,提升了并行测试效率,降低了资源占用,有效地缩短了测试时间。
