Higher-s dielectric LaLuO3, deposited by molecular beam deposition, with TiN as gate stack is integrated into high-mobility Si/SiGe/SOI quantum-well p-type metal-oxide-semiconduetor field effect transistors. Threshold...Higher-s dielectric LaLuO3, deposited by molecular beam deposition, with TiN as gate stack is integrated into high-mobility Si/SiGe/SOI quantum-well p-type metal-oxide-semiconduetor field effect transistors. Threshold voltage shift and capacitance equivalent thickness shrink are observed, resulting from oxygen scavenging effect in LaLuO3 with ti-rich TiN after high temperature annealing. The mechanism of oxygen scavenging and its potential for resistive memory applications are analyzed and discussed.展开更多
在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以...在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 。展开更多
The large current effect of silicon germanium heterojunction bipolar transistors fabricated on thin silicon-on-insulator is included in the model.As the current is two-dimensional,the injection for large current is ve...The large current effect of silicon germanium heterojunction bipolar transistors fabricated on thin silicon-on-insulator is included in the model.As the current is two-dimensional,the injection for large current is vertical plus horizontal and is quite different from that of the bulk device.Critical parameters modeling the large current,such as the collector injection width,the hole density and the corresponding potential in the injection region,are discussed,and the influence to the transit time is also analyzed.展开更多
The product of the cutoff frequency and breakdown voltage （fT x BVCEo） is an important figure of merit （FOM） to characterize overall performance of heterojunction bipolar transistor （HBT）. In this paper, an appr...The product of the cutoff frequency and breakdown voltage （fT x BVCEo） is an important figure of merit （FOM） to characterize overall performance of heterojunction bipolar transistor （HBT）. In this paper, an approach to introducing a thin N＋-buried layer into N collector region in silicon-on-insulator （SOI） SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional （2D） numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOl structure, the effects of SOI insulation layer thickness （TBox） on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fw, slightly increases BVcEO to some extent, but ultimately degrades the FOM of fTXBVcEo. Although the fT, BVcEo, and the FOM of fTXBVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiOa layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N＋-buried layer is introduced into collector region to not only improve the FOM of fT ×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N＋-buried layer in collector region is investigated in detail. The result show that the FOM of fT xBVcEo is improved and the device temperature decreases as the N＋-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N＋-buried layer into collector region provides an effective method to improve SOI SiGe HBT overall performance.展开更多
基金Supported by the National Natural Science Foundation of China under Grant No 61306126
文摘Higher-s dielectric LaLuO3, deposited by molecular beam deposition, with TiN as gate stack is integrated into high-mobility Si/SiGe/SOI quantum-well p-type metal-oxide-semiconduetor field effect transistors. Threshold voltage shift and capacitance equivalent thickness shrink are observed, resulting from oxygen scavenging effect in LaLuO3 with ti-rich TiN after high temperature annealing. The mechanism of oxygen scavenging and its potential for resistive memory applications are analyzed and discussed.
文摘在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 。
基金Supported by the Pre-research Foundation from the National Ministries and Commissions of China(Nos 51308030201 and 9140A080509DZ0106).
文摘The large current effect of silicon germanium heterojunction bipolar transistors fabricated on thin silicon-on-insulator is included in the model.As the current is two-dimensional,the injection for large current is vertical plus horizontal and is quite different from that of the bulk device.Critical parameters modeling the large current,such as the collector injection width,the hole density and the corresponding potential in the injection region,are discussed,and the influence to the transit time is also analyzed.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61574010,60776051,61006059,and 61006044)the Beijing Municipal Natural Science Foundation,China(Grant No.4142007)the Beijing Municipal Education Committee,China(Grant No.KM200910005001)
文摘The product of the cutoff frequency and breakdown voltage （fT x BVCEo） is an important figure of merit （FOM） to characterize overall performance of heterojunction bipolar transistor （HBT）. In this paper, an approach to introducing a thin N＋-buried layer into N collector region in silicon-on-insulator （SOI） SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional （2D） numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOl structure, the effects of SOI insulation layer thickness （TBox） on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fw, slightly increases BVcEO to some extent, but ultimately degrades the FOM of fTXBVcEo. Although the fT, BVcEo, and the FOM of fTXBVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiOa layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N＋-buried layer is introduced into collector region to not only improve the FOM of fT ×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N＋-buried layer in collector region is investigated in detail. The result show that the FOM of fT xBVcEo is improved and the device temperature decreases as the N＋-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N＋-buried layer into collector region provides an effective method to improve SOI SiGe HBT overall performance.
