A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor shari...A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.展开更多
The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator ...The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.展开更多
为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提...为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm^2。ADC的微分非线性和积分非线性分别小于0.36最低有效位(LSB)和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 Msample/s。运行频率为230 Msample/s和260 Msample/s的ADC的功率消耗分别为13.9 m W和17.8 m W。展开更多
设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路。该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的"外推",减小了第二级支路所需的电流...设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路。该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的"外推",减小了第二级支路所需的电流,并达到了更大的单位增益带宽。该电路运用于一种12 bit 250 MS/s流水线ADC的各级余量增益放大器(MDAC),并采用0.18μm 1P5M 1.8 V CMOS工艺实现。测试结果表明,该ADC电路在全速采样条件下对于20 MHz的输入信号得到的信噪比(SNR)为69.92 d B,无杂散动态范围(SFDR)为81.17 d B,整个ADC电路的功耗为320 m W。展开更多
介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率...介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率之间的折中选择。采用了时间交织、流水线和运算放大器共享等技术,既提高了速度和精度,也节省了功耗。同时为了减小时序失配对时间交织流水线ADC性能的影响,提出了一种对时序扭曲不敏感的采样保持电路。采用SMIC0.13μm CMOS工艺进行了电路设计,核心电路面积为1.6 mm×1.3 mm。测试结果表明,在采样速率为200 MS/s、模拟输入信号频率为1 MHz时,无杂散动态范围(SFDR)可以达到67.8 d B,信噪失真比(SNDR)为55.7 d B,ADC的品质因子(Fo M)为1.07 p J/conv.,而功耗为107 m W。展开更多
A bunch arrival-time monitor(BAM) system,based on electro-optical intensity modulation scheme, is under study at Shanghai Soft X-ray Free Electron Laser.The aim of the study is to achieve high-precision time measureme...A bunch arrival-time monitor(BAM) system,based on electro-optical intensity modulation scheme, is under study at Shanghai Soft X-ray Free Electron Laser.The aim of the study is to achieve high-precision time measurement for minimizing bunch fluctuations. A readout electronics is developed to fulfill the requirements of the BAM system. The readout electronics is mainly composed of a signal conditioning circuit, field-programmable gate array(FPGA), mezzanine card(FMC150), and powerful FPGA carrier board. The signal conditioning circuit converts the laser pulses into electrical pulse signals using a photodiode. Thereafter, it performs splitting and low-noise amplification to achieve the best voltage sampling performance of the dual-channel analog-to-digital converter(ADC) in FMC150. The FMC150 ADC daughter card includes a 14-bit 250 Msps dual-channel high-speed ADC,a clock configuration, and a management module. The powerful FPGA carrier board is a commercial high-performance Xilinx Kintex-7 FPGA evaluation board. To achieve clock and data alignment for ADC data capture at a high sampling rate, we used ISERDES, IDELAY, and dedicated carry-in resources in the Kintex-7 FPGA. This paper presents a detailed development of the readout electronics in the BAM system and its performance.展开更多
Neural signal can be used for clinical disease diagnosis,data analysis and real-time life signal monitoring.Its analysis requires high-performance signal processors.Based on the 180 nm standard CMOS technology,a16-cha...Neural signal can be used for clinical disease diagnosis,data analysis and real-time life signal monitoring.Its analysis requires high-performance signal processors.Based on the 180 nm standard CMOS technology,a16-channel fully-differential neural recording chip is designed.The chip consists of 16-channel low-noise pre-amplifiers,a multiplexer and a successive approximation register（SAR）ADC.The result shows that the equivalent input-referred noise of recording amplifier is 3.63μV,bringing down noise efficiency factor to 4.24.At 8.5 bits effective number of bit（ENOB）,the analog-to-digital converter（ADC）has an SNR of 52.6dB.The core area of the proposed neural recording front-end is about 2.46 mm^2.展开更多
基金supported by the Major National Science & Technology Program of China under Grant No.2012ZX03004004-002National High Technology Research and Development Program of China under Grant No. 2013AA014302
文摘A low-power 14-bit 150MS/s an- alog-to-digital converter （ADC） is present- ed for communication applications. Range scaling enables a maximal 2-Vp-p input with a single-stage opamp adopted. Opamp and capacitor sharing between the first multi- plying digital-to-analog converter （MDAC） and the second one reduces the total opamp power further. The dedicated sample-and- hold amplifier （SHA） is removed to lower the power and the noise. The blind calibration of linearity errors is proposed to improve the per- formance. The prototype ADC is fabricated in a 130rim CMOS process with a 1.3-V supply voltage. The SNDR of the ADC is 71.3 dB with a 2.4 MHz input and remains 68.5 dB for a 120 MHz input. It consumes 85 roW, which includes 57 mW for the ADC core, 11 mW for the low jitter clock receiver and 17 mW for the high-speed reference buffer.
基金Supported by the National Natural Science Foundation of China (No. 60072004)
文摘The effects of stage numbers on power dissipation of pipeline analog-to-digital converter （ADC） are studied and a novel design method aiming for power optimization is presented. In this method, a minimum comparator number algorithm （MCNA） is first introduced, and then the optimum distribution of resolutions through pipeline ADC stages is deduced by MCNA. Based on the optimum stage-resolution distribution, an optimization method is established, which examines the precise function between ADC power and stage resolutions with a parameter of power ratio （Rp）. For 10-bit pipeline ADC with scaling down technology, the simulation results by using MATLAB CAD tools show that an eight-stage topology with 1-bit RSD correction achieves the power optimization indicated by the power reduction ratio.
文摘为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型(SAR)模数转换器(ADC)。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm^2。ADC的微分非线性和积分非线性分别小于0.36最低有效位(LSB)和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 Msample/s。运行频率为230 Msample/s和260 Msample/s的ADC的功率消耗分别为13.9 m W和17.8 m W。
文摘设计了一种应用于12 bit 250 MS/s采样频率的流水线模数转换器(ADC)的运算放大器电路。该电路采用全差分两级结构以达到足够的增益和信号摆幅;采用一种改进的频率米勒补偿方法实现次极点的"外推",减小了第二级支路所需的电流,并达到了更大的单位增益带宽。该电路运用于一种12 bit 250 MS/s流水线ADC的各级余量增益放大器(MDAC),并采用0.18μm 1P5M 1.8 V CMOS工艺实现。测试结果表明,该ADC电路在全速采样条件下对于20 MHz的输入信号得到的信噪比(SNR)为69.92 d B,无杂散动态范围(SFDR)为81.17 d B,整个ADC电路的功耗为320 m W。
文摘以TSMC0.18μmCMOS制程实现10位元(10-bit)、每秒取样2×107次、操作电压1.8 V的管线式(pipe-line)模拟数字转换器(ADC)芯片。本设计主要是使用1.5-bit/stage架构,并且配合运算放大器(op amp)共享(sharing)技术,拔除传统第一级取样保持放大器(SHA,sample and hold amplifier)以节省功耗。此芯片的量测结果为输入信号频率2 MHz时,输出的SNDR与ENOB各为46.2 dB与7.32-bit,包含焊线垫片(pad)的芯片面积为1.54(1.391×1.107)mm2,芯片功耗为29.2 mW。
文摘介绍了一款应用于无线收发系统的12 bit 200 MS/s的A/D转换器(ADC)。流水线型模数转换器是从中频采样到高频采样并且具有高精度的典型结构,多个流水线型模数转换器利用时间交织技术合并成一个模数转换器的构想则是复杂结构和能量利用率之间的折中选择。采用了时间交织、流水线和运算放大器共享等技术,既提高了速度和精度,也节省了功耗。同时为了减小时序失配对时间交织流水线ADC性能的影响,提出了一种对时序扭曲不敏感的采样保持电路。采用SMIC0.13μm CMOS工艺进行了电路设计,核心电路面积为1.6 mm×1.3 mm。测试结果表明,在采样速率为200 MS/s、模拟输入信号频率为1 MHz时,无杂散动态范围(SFDR)可以达到67.8 d B,信噪失真比(SNDR)为55.7 d B,ADC的品质因子(Fo M)为1.07 p J/conv.,而功耗为107 m W。
基金supported by the National Key R&D Plan(No.2016YFA0401900)
文摘A bunch arrival-time monitor(BAM) system,based on electro-optical intensity modulation scheme, is under study at Shanghai Soft X-ray Free Electron Laser.The aim of the study is to achieve high-precision time measurement for minimizing bunch fluctuations. A readout electronics is developed to fulfill the requirements of the BAM system. The readout electronics is mainly composed of a signal conditioning circuit, field-programmable gate array(FPGA), mezzanine card(FMC150), and powerful FPGA carrier board. The signal conditioning circuit converts the laser pulses into electrical pulse signals using a photodiode. Thereafter, it performs splitting and low-noise amplification to achieve the best voltage sampling performance of the dual-channel analog-to-digital converter(ADC) in FMC150. The FMC150 ADC daughter card includes a 14-bit 250 Msps dual-channel high-speed ADC,a clock configuration, and a management module. The powerful FPGA carrier board is a commercial high-performance Xilinx Kintex-7 FPGA evaluation board. To achieve clock and data alignment for ADC data capture at a high sampling rate, we used ISERDES, IDELAY, and dedicated carry-in resources in the Kintex-7 FPGA. This paper presents a detailed development of the readout electronics in the BAM system and its performance.
基金Supported by the National Natural Science Foundation of China(61301006,61271113)
文摘Neural signal can be used for clinical disease diagnosis,data analysis and real-time life signal monitoring.Its analysis requires high-performance signal processors.Based on the 180 nm standard CMOS technology,a16-channel fully-differential neural recording chip is designed.The chip consists of 16-channel low-noise pre-amplifiers,a multiplexer and a successive approximation register（SAR）ADC.The result shows that the equivalent input-referred noise of recording amplifier is 3.63μV,bringing down noise efficiency factor to 4.24.At 8.5 bits effective number of bit（ENOB）,the analog-to-digital converter（ADC）has an SNR of 52.6dB.The core area of the proposed neural recording front-end is about 2.46 mm^2.
