The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of re configurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented...The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of re configurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented. Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of 'hardware' function that can be called by the DSP in high-level algorithm. It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.展开更多
Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at t...Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.展开更多
A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity...A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity of contemporary high-performance spacecraft processors.To harness these non-uniform access behaviors,an efficient cache replacement framework featuring an auxiliary cache specifically designed to retain evicted hot data was proposed.This framework reconstructs the cache replacement policy,facilitating data migration between the main cache and the auxiliary cache.Unlike traditional cacheline-granularity policies,the approach excels at identifying and evicting infrequently used data,thereby optimizing cache utilization.The evaluation shows impressive performance improvement,especially on workloads with irregular access patterns.Benefiting from fine granularity,the proposal achieves superior storage efficiency compared with commonly used cache management schemes,providing a potential optimization opportunity for modern resource-constrained processors,such as spacecraft processors.Furthermore,the framework complements existing modern cache replacement policies and can be seamlessly integrated with minimal modifications,enhancing their overall efficacy.展开更多
目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频...目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频率调节(Dynamic Voltage Frequency Scaling,DVFS)技术,研究异构多核实时系统中基于任务同步的节能调度问题,提出同步感知的最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First,SA-LESF)。该算法针对所有任务的速度配置进行迭代优化,直至所有任务均达到其最大限度节能的速度配置。此外,进一步提出基于动态松弛时间回收的同步感知最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First with Dynamic Reclamation,SA-LESF-DR)。该算法在保证实时任务可调度的同时,实施相应的回收策略,进一步降低系统能耗。实验结果表明,SA-LESF与SA-LESF-DR算法在能耗表现上具有优势,在相同任务集下,相比其他算法可节省高达30%的能耗。展开更多
Fortran语言在科学与工程计算领域具有广泛应用。然而,通用数字信号处理器(General-Purpose Digital Signal Processor,GPDSP)目前主要使用C语言或汇编语言进行编程,尚不支持Fortran语言。针对这一现状,面向CPU-DSP异构处理器的Fortran...Fortran语言在科学与工程计算领域具有广泛应用。然而,通用数字信号处理器(General-Purpose Digital Signal Processor,GPDSP)目前主要使用C语言或汇编语言进行编程,尚不支持Fortran语言。针对这一现状,面向CPU-DSP异构处理器的Fortran编译器实现技术,基于LLVM Flang编译器框架设计并实现了Fortran编译器原型mtFortran,完成了Flang前端移植,并重点解决了Fortran程序在异构架构上的编译和运行支持,包括加载执行、语法支持、内建函数实现及输入输出(I/O)系统适配问题。实验结果表明,该Fortran编译器成功支持Fortran语言商用测试集U_F90_TS_LITE中GUIDE F90测试集的语法特性,在176个测试程序中运行时库已完全支持的测试程序(102道)全部通过异构编译与加载执行验证,主要类别内建函数的实现率达79.38%,并可支持典型高性能计算程序的运行(如NPB-EP测试程序),实现了Fortran程序在CPU-DSP异构处理器架构上的基础运行能力,为后续完善标准支持、性能优化及并行化扩展奠定了基础。展开更多
文摘The concept and advantage of reconfigurable technology is introduced. A kind of processor architecture of re configurable macro processor (RMP) model based on FPGA array and DSP is put forward and has been implemented. Two image algorithms are developed: template-based automatic target recognition and zone labeling. One is estimating for motion direction in the infrared image background, another is line picking-up algorithm based on image zone labeling and phase grouping technique. It is a kind of 'hardware' function that can be called by the DSP in high-level algorithm. It is also a kind of hardware algorithm of the DSP. The results of experiments show the reconfigurable computing technology based on RMP is an ideal accelerating means to deal with the high-speed image processing tasks. High real time performance is obtained in our two applications on RMP.
基金Project(2008AA01A201) supported the National High-tech Research and Development Program of ChinaProjects(60833004, 60633050) supported by the National Natural Science Foundation of China
文摘Developing parallel applications on heterogeneous processors is facing the challenges of 'memory wall',due to limited capacity of local storage,limited bandwidth and long latency for memory access. Aiming at this problem,a parallelization approach was proposed with six memory optimization schemes for CG,four schemes of them aiming at all kinds of sparse matrix-vector multiplication (SPMV) operation. Conducted on IBM QS20,the parallelization approach can reach up to 21 and 133 times speedups with size A and B,respectively,compared with single power processor element. Finally,the conclusion is drawn that the peak bandwidth of memory access on Cell BE can be obtained in SPMV,simple computation is more efficient on heterogeneous processors and loop-unrolling can hide local storage access latency while executing scalar operation on SIMD cores.
文摘A notable portion of cachelines in real-world workloads exhibits inner non-uniform access behaviors.However,modern cache management rarely considers this fine-grained feature,which impacts the effective cache capacity of contemporary high-performance spacecraft processors.To harness these non-uniform access behaviors,an efficient cache replacement framework featuring an auxiliary cache specifically designed to retain evicted hot data was proposed.This framework reconstructs the cache replacement policy,facilitating data migration between the main cache and the auxiliary cache.Unlike traditional cacheline-granularity policies,the approach excels at identifying and evicting infrequently used data,thereby optimizing cache utilization.The evaluation shows impressive performance improvement,especially on workloads with irregular access patterns.Benefiting from fine granularity,the proposal achieves superior storage efficiency compared with commonly used cache management schemes,providing a potential optimization opportunity for modern resource-constrained processors,such as spacecraft processors.Furthermore,the framework complements existing modern cache replacement policies and can be seamlessly integrated with minimal modifications,enhancing their overall efficacy.
文摘目前,多核实时系统中同步任务的节能调度研究主要针对的是同构多核处理器平台,而异构多核处理器架构能够更有效地发挥系统性能。将现有的研究直接应用于异构多核系统,在保证可调度性的情况下会导致能耗变高。对此,通过使用动态电压与频率调节(Dynamic Voltage Frequency Scaling,DVFS)技术,研究异构多核实时系统中基于任务同步的节能调度问题,提出同步感知的最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First,SA-LESF)。该算法针对所有任务的速度配置进行迭代优化,直至所有任务均达到其最大限度节能的速度配置。此外,进一步提出基于动态松弛时间回收的同步感知最大能耗节省优先算法(Synchronization Aware-Largest Energy Saved First with Dynamic Reclamation,SA-LESF-DR)。该算法在保证实时任务可调度的同时,实施相应的回收策略,进一步降低系统能耗。实验结果表明,SA-LESF与SA-LESF-DR算法在能耗表现上具有优势,在相同任务集下,相比其他算法可节省高达30%的能耗。
文摘Fortran语言在科学与工程计算领域具有广泛应用。然而,通用数字信号处理器(General-Purpose Digital Signal Processor,GPDSP)目前主要使用C语言或汇编语言进行编程,尚不支持Fortran语言。针对这一现状,面向CPU-DSP异构处理器的Fortran编译器实现技术,基于LLVM Flang编译器框架设计并实现了Fortran编译器原型mtFortran,完成了Flang前端移植,并重点解决了Fortran程序在异构架构上的编译和运行支持,包括加载执行、语法支持、内建函数实现及输入输出(I/O)系统适配问题。实验结果表明,该Fortran编译器成功支持Fortran语言商用测试集U_F90_TS_LITE中GUIDE F90测试集的语法特性,在176个测试程序中运行时库已完全支持的测试程序(102道)全部通过异构编译与加载执行验证,主要类别内建函数的实现率达79.38%,并可支持典型高性能计算程序的运行(如NPB-EP测试程序),实现了Fortran程序在CPU-DSP异构处理器架构上的基础运行能力,为后续完善标准支持、性能优化及并行化扩展奠定了基础。
文摘仿真点(simulation point,SimPoint)作为一种代表性采样技术被广泛应用于处理器硅前性能评估中。SimPoint为每个待评估的程序根据贝叶斯信息准则确定仿真点数目。然而,标准测试集内不同程序有着不同的行为复杂程度,需要不同数目的仿真点来准确刻画其程序行为。SimPoint无法识别出不同程序间的复杂度差异,无法做到在总仿真点数目一定的情况下,将更多的仿真点分配给行为复杂的程序以降低这些程序的性能评估误差,将更少的仿真点分配给行为简单的程序而不损失这些程序的性能评估精度。由于没有在测试集内合理地进行仿真点分配,SimPoint虽然可以给出比较准确的平均性能评估误差,但是某些行为复杂的测试子项的性能评估误差依然较大。针对这一问题,本文优化了SimPoint的仿真点局部分配方式,提出了一种全局贪心分配方法———贪心点(greedy point,GreedyPoint)方法。该方法将仿真点的分配问题抽象为含约束的优化问题,使用微架构无关特征计算表征误差,通过全局贪心算法来求解该优化问题。实验数据表明,在相同仿真开销下,与SimPoint相比,GreedyPoint可以将SPEC CPU 2017测试套件的平均性能评估误差由3.23%降低到2.08%,最大性能评估误差由21.22%大幅降低至7.01%。
