To mitigate the impact of noise and inter-ference on multi-level-cell(MLC)flash memory with the use of low-density parity-check(LDPC)codes,we propose a dynamic write-voltage design scheme con-sidering the asymmetric p...To mitigate the impact of noise and inter-ference on multi-level-cell(MLC)flash memory with the use of low-density parity-check(LDPC)codes,we propose a dynamic write-voltage design scheme con-sidering the asymmetric property of raw bit error rate(RBER),which can obtain the optimal write voltage by minimizing a cost function.In order to further improve the decoding performance of flash memory,we put forward a low-complexity entropy-based read-voltage optimization scheme,which derives the read voltages by searching for the optimal entropy value via a log-likelihood ratio(LLR)-aware cost function.Simulation results demonstrate the superiority of our proposed dynamic write-voltage design scheme and read-voltage optimization scheme with respect to the existing counterparts.展开更多
为了提高MLC NAND Flash的抗误码性能,该文提出一种基于优化缩短极化码的MLC NAND Flash差错控制方法。优化缩短极化码通过优化删减图样得到,首先通过比特翻转重排序的方式得到基本删减图样,进而选择具有更低信道容量的冻结比特组成优...为了提高MLC NAND Flash的抗误码性能,该文提出一种基于优化缩短极化码的MLC NAND Flash差错控制方法。优化缩短极化码通过优化删减图样得到,首先通过比特翻转重排序的方式得到基本删减图样,进而选择具有更低信道容量的冻结比特组成优化删减图样,使得到的删减比特全为冻结比特,可以显著提高删减算法的纠错性能。同时,根据MLC单元错误的不对称性,采用码率自适应的码字对FLASH中MSB和LSB进行不等错误保护。仿真结果表明:当误帧率为310-时,优化缩短极化码较相同码长的LDPC码和基本缩短极化码分别约有3.72~5.89 d B和1.47~3.49 d B增益;相比基于同一码率的优化缩短极化码方案,不等错误保护的差错控制方案获得约0.25 d B增益。展开更多
基金supported in part by the NSF of China under Grants 62322106,62071131,U2001203,61871136the Guangdong Basic and Applied Basic Research Foundation under Grant 2022B1515020086+1 种基金the International Collaborative Research Program of Guangdong Science and Technology Department under Grant 2022A0505050070the Industrial R&D Project of Haoyang Electronic Co.,Ltd.under Grant 2022440002001494.
文摘To mitigate the impact of noise and inter-ference on multi-level-cell(MLC)flash memory with the use of low-density parity-check(LDPC)codes,we propose a dynamic write-voltage design scheme con-sidering the asymmetric property of raw bit error rate(RBER),which can obtain the optimal write voltage by minimizing a cost function.In order to further improve the decoding performance of flash memory,we put forward a low-complexity entropy-based read-voltage optimization scheme,which derives the read voltages by searching for the optimal entropy value via a log-likelihood ratio(LLR)-aware cost function.Simulation results demonstrate the superiority of our proposed dynamic write-voltage design scheme and read-voltage optimization scheme with respect to the existing counterparts.
文摘为了提高MLC NAND Flash的抗误码性能,该文提出一种基于优化缩短极化码的MLC NAND Flash差错控制方法。优化缩短极化码通过优化删减图样得到,首先通过比特翻转重排序的方式得到基本删减图样,进而选择具有更低信道容量的冻结比特组成优化删减图样,使得到的删减比特全为冻结比特,可以显著提高删减算法的纠错性能。同时,根据MLC单元错误的不对称性,采用码率自适应的码字对FLASH中MSB和LSB进行不等错误保护。仿真结果表明:当误帧率为310-时,优化缩短极化码较相同码长的LDPC码和基本缩短极化码分别约有3.72~5.89 d B和1.47~3.49 d B增益;相比基于同一码率的优化缩短极化码方案,不等错误保护的差错控制方案获得约0.25 d B增益。
