Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high perfor...Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.展开更多
基金Supported by the National Natural Science Foundation of China(No.60576066,No.60644007)the Natural Science Foundation of Anhui Province(No.2006kj012a).
基金Project supported by Key Project of National Natural Science Foundation of China（50531060） National Science Found for Distinguished Young Scholars of China（10525211）+2 种基金 National Natural Science Foundation of China（10572124 10472099） Key Project of Scientific and Technological Department of Hunan Province （05FJ2005）, and the Open Project Program of Low Dimensional Materials ＆ Application Technology （Xiangtan University）, Ministry of Education, China （KF0602）.
文摘Growing a silicon(Si) layer on top of stacked Si-germanium(Ge) compressive layer can introduce a tensile strain on the former, resulting in superior device characteristics. Such a structure can be used for high performance complementary metal-oxide-semiconductor(CMOS) circuits. Down scaling metal-oxide-semiconductor field-effect transistors(MOSFETs) into the deep submicron/nanometer regime forces the source(S) and drain(D) series resistance to become comparable with the channel resistance and thus it cannot be neglected. Owing to the persisting technological importance of strained Si devices, in this work, we propose a multi-iterative technique for evaluating the performance of strained-Si/strained-Si_(1-y)Ge_y/relaxed-Si_(1-x)Ge_x MOSFETs and its related circuits in the presence of S/D series resistance, leading to the development of a simulator that can faithfully plot the performance of the device and related digital circuits. The impact of strain on device/circuit performance is also investigated with emphasis on metal gate and high-k dielectric materials.
