In this paper, the Cauchy type integral for M-analytic function is investigated which is by definition the regular solution of the elliptic system f_x+Mf_y=0, where M is a constant m×m matrix without any real eig...In this paper, the Cauchy type integral for M-analytic function is investigated which is by definition the regular solution of the elliptic system f_x+Mf_y=0, where M is a constant m×m matrix without any real eigenvalues and f is an m×q matrix.展开更多
An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields...An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.展开更多
基金This work is supported in part by the National Natural Science Foundation of China.
文摘In this paper, the Cauchy type integral for M-analytic function is investigated which is by definition the regular solution of the elliptic system f_x+Mf_y=0, where M is a constant m×m matrix without any real eigenvalues and f is an m×q matrix.
文摘An application specific integrated circuit (ASIC) design of a 1024 points floating-point fast Fourier transform(FFT) processor is presented. It can satisfy the requirement of high accuracy FFT result in related fields. Several novel design techniques for floating-point adder and multiplier are introduced in detail to enhance the speed of the system. At the same time, the power consumption is decreased. The hardware area is effectively reduced as an improved butterfly processor is developed. There is a substantial increase in the performance of the design since a pipelined architecture is adopted, and very large scale integrated (VLSI) is easy to realize due to the regularity. A result of validation using field programmable gate array (FPGA) is shown at the end. When the system clock is set to 50 MHz, 204.8 μs is needed to complete the operation of FFT computation.
