A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system contr...A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.展开更多
A complete method of synchronization technology of bistatic radar using global position system （GPS） is presented. The pulse per second signal （1PPS） is elaborately modified to increase the time synchronization pr...A complete method of synchronization technology of bistatic radar using global position system （GPS） is presented. The pulse per second signal （1PPS） is elaborately modified to increase the time synchronization precision and keep loop locking. A very high time synchronization precision is achieved. Using the modified 1PPS to discipline the local OCXO, the reference frequency signal achieves both high long term stability （LTS） and short term stability （STS） properties. An algorithm, named phase abrupt change CFAR is presented to restrain the 1PPS phase abrupt change and keep loop locking. The experimental results indicate that this time and frequency synchronization method is effective and the time synchronization precision of the synchronization system can be improved from ±100 ns to ±25 ns. In addition, the phase noise is improved to 20 dB.展开更多
基金Project(2011912004)supported by the Major Program of the Economic & Information Commission Program of Guangdong Province,ChinaProjects(2011B010700065,2011A090200106)supported by the Major Program of the Department of Science and Technology of Guangdong Province,China
文摘A 2.7-4.0 GHz dual-mode auto frequency calibration(AFC) fast locking PLL was designed for navigation system on chip(SoC). The SoC was composed of one radio frequency(RF) receiver, one baseband and several system control parts. In the proposed AFC block, both analog and digital modes were designed to complete the AFC process. In analog mode, the analog part sampled and detected the charge pump output tuning voltage, which would give the indicator to digital part to adjust the voltage control oscillator(VCO) capacitor bank. In digital mode, the digital part counted the phase lock loop(PLL) divided clock to judge whether VCO frequency was fast or slow. The analog and digital modes completed the auto frequency calibration function independently by internal switch. By designing a special switching algorithm, the switch of the digital and analog mode could be realized anytime during the lock and unlock detecting process for faster and more stable locking. This chip is fabricated in 0.13 μm RF complementary metal oxide semiconductor(CMOS) process, and the VCO supports the frequency range from 2.7 to 4.0 GHz. Tested 3.96 GHz frequency phase noise is -90 d Bc/Hz@100 k Hz frequency offset and -120 d Bc/Hz@1 MHz frequency offset. By using the analog mode in lock detection and digital mode in unlock detection, tested AFC time is less than 9 μs and the total PLL lock time is less than 19 μs. The SoC acquisition and tracking sensitivity are about-142 d Bm and-155 d Bm, respectively. The area of the proposed PLL is 0.35 mm^2 and the total SoC area is about 9.6 mm^2.
基金the National Ministry Innovation Foundation (7130302)
文摘A complete method of synchronization technology of bistatic radar using global position system （GPS） is presented. The pulse per second signal （1PPS） is elaborately modified to increase the time synchronization precision and keep loop locking. A very high time synchronization precision is achieved. Using the modified 1PPS to discipline the local OCXO, the reference frequency signal achieves both high long term stability （LTS） and short term stability （STS） properties. An algorithm, named phase abrupt change CFAR is presented to restrain the 1PPS phase abrupt change and keep loop locking. The experimental results indicate that this time and frequency synchronization method is effective and the time synchronization precision of the synchronization system can be improved from ±100 ns to ±25 ns. In addition, the phase noise is improved to 20 dB.
