In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product uni...In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.展开更多
该文提出了一种应用于移动顶点处理器的高性能低功耗定点特殊函数运算单元电路。该运算单元支持嵌入式图形标准OpenGL ES 1.X的定点数据格式,并支持小数点后16位精度的倒数、均方根、倒数均方根、对数和指数等初等函数运算。初等函数采...该文提出了一种应用于移动顶点处理器的高性能低功耗定点特殊函数运算单元电路。该运算单元支持嵌入式图形标准OpenGL ES 1.X的定点数据格式,并支持小数点后16位精度的倒数、均方根、倒数均方根、对数和指数等初等函数运算。初等函数采用分段二次多项式插值方法近似计算,系数处理中引入2运算电路,相对于传统的设计在相同的精度下使整体的二次多项式查找表大小减少了29%。优化二次多项式插值算法的计算误差和截断误差,使电路的查找表大小、平方器、乘法器和加法器的面积、速度达到最优。该电路采用0.18μm的CMOS工艺实现,面积为0.112 mm2,芯片时钟频率达到300 MHz,功耗仅为12.8 mW。测试结果表明该定点特殊函数运算单元非常适合移动图形顶点处理器的初等函数计算应用。展开更多
文摘In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time(DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.
