In this manuscript,the perovskite-based metal–oxide–semiconductor field effect transistors（MOSFETs） with phenylC61-butyric acid methylester（PCBM） layers are studied.The MOSFETs are fabricated on perovskites,and ...In this manuscript,the perovskite-based metal–oxide–semiconductor field effect transistors（MOSFETs） with phenylC61-butyric acid methylester（PCBM） layers are studied.The MOSFETs are fabricated on perovskites,and characterized by photoluminescence spectra（PL）,x-ray diffraction（XRD）,and x-ray photoelectron spectroscopy（XPS）.With PCBM layers,the current–voltage hysteresis phenomenon is effetely inhibited,and both the transfer and output current values increase.The band energy diagrams are proposed,which indicate that the electrons are transferred into the PCBM layer,resulting in the increase of photocurrent.The electron mobility and hole mobility are extracted from the transfer curves,which are about one order of magnitude as large as those of PCBM deposited,which is the reason why the electrons are transferred into the PCBM layer and the holes are still in the perovskites,and the effects of ionized impurity scattering on carrier transport become smaller.展开更多
A facile approach was demonstrated for fabricating high-performance nonvolatile memory devices based on ferroelectric-gate field effect transistors using a p-type Si nanowire coated with omega-shaped gate organic ferr...A facile approach was demonstrated for fabricating high-performance nonvolatile memory devices based on ferroelectric-gate field effect transistors using a p-type Si nanowire coated with omega-shaped gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene)(P(VDF-Tr FE)). We overcame the interfacial layer problem by incorporating P(VDF-Tr FE) as a ferroelectric gate using a low-temperature fabrication process. Our memory devices exhibited excellent memory characteristics with a low programming voltage of ±5 V, a large modulation in channel conductance between ON and OFF states exceeding 105, a long retention time greater than 3 9 104 s, and a high endurance of over 105 programming cycles while maintaining an ION/IOFFratio higher than 102.展开更多
The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is o...The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus （BP） by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10 V/nm to 0.83 V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronies, thermoelectric power generation and thermal imaging.展开更多
The temperature-dependent effect of residual charge carrier （no）, at the Dirac point, on mobility is studied. We fabricate and characterize a graphene field effect transistor （GFET） using 7nm TiO2 as the top-gate ...The temperature-dependent effect of residual charge carrier （no）, at the Dirac point, on mobility is studied. We fabricate and characterize a graphene field effect transistor （GFET） using 7nm TiO2 as the top-gate dielectric. The temperature-dependent gate voltage-drain current and room temperature gate capacitance are measured to extract the carrier mobility and to estimate the quantum capacitance of the GFET. The device shows the mobility value of gOO cm^2 /V.s at room temperature and it decreases to 45 cm^2 /V.s for 20 K due to the increase of n0. These results indicate that the phonon scattering is not the dominant process for the unevenness dielectric layer while the coulomb scattering by charged impurities degrades the device characteristically at low temperature.展开更多
We report a novel structure of A1GaN/GaN heterostructure field effect transistors （HFETs） with a Si and Mg pair- doped interlayer grown on Si substrate. By optimizing the doping concentrations of the pair-doped inte...We report a novel structure of A1GaN/GaN heterostructure field effect transistors （HFETs） with a Si and Mg pair- doped interlayer grown on Si substrate. By optimizing the doping concentrations of the pair-doped interlayers, the mobility of 2DEG increases by twice for the conventional structure under 5 K due to the improved crystalline quality of the conduction channel. The proposed HFET shows a four orders lower off-state leakage current, resulting in a much higher on/off ratio （ - 10^9）. Further temperature-dependent performance of Schottky diodes revealed that the inhibition of shallow surface traps in proposed HFETs should be the main reason for the suppression of leakage current.展开更多
Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL （drain induced barrier lowering） effect for short channel 4H-SiC metal...Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL （drain induced barrier lowering） effect for short channel 4H-SiC metal semiconductor field effect transistors （MESFETs）. An accurate analytical model of threshold voltage shift for the asymmetric short channel 4H-SiC MESFET is presented and thus verified. According to the presented model, it analyses the threshold voltage for short channel device on the L/a （channel length/channel depth） ratio, drain applied voltage VDS and channel doping concentration ND, thus providing a good basis for the design and modelling of short channel 4H-SiC MESFETs device.展开更多
This paper proposes an effective method of fabricating top contact organic field effect transistors by using a pho- tolithographic process. The semiconductor layer is protected by a passivation layer. Through photolit...This paper proposes an effective method of fabricating top contact organic field effect transistors by using a pho- tolithographic process. The semiconductor layer is protected by a passivation layer. Through photolithographic and etching processes, parts of the passivation layer are etched off to form source/drain electrode patterns. Combined with conventional evaporation and lift-off techniques, organic field effect transistors with a top contact are fabricated suc- cessfully, whose properties are comparable to those prepared with the shadow mask method and one order of magnitude higher than the bottom contact devices fabricated by using a photolithographic process.展开更多
A simple and effective approach to improve the switching characteristics of AlGaN/AlN/GaN heterostructure field effect transistors （HFETs） by applying a voltage bias on the substrate is presented. With the increase ...A simple and effective approach to improve the switching characteristics of AlGaN/AlN/GaN heterostructure field effect transistors （HFETs） by applying a voltage bias on the substrate is presented. With the increase of the substrate bias, the OFF-state drain current is much reduced and the ON-state current keeps constant. Both the ON/OFF current ratio and the subthreshold swing are demonstrated to be greatly improved. With the thinned substrate, the improvement of the switching characteristics with the substrate bias is found to be even greater. The above improvements of the switching characteristics are attributed to the interaction between the substrate bias induced electrical field and the bulk traps in the GaN buffer layer, which reduces the conductivity of the GaN buffer layer.展开更多
An analytical model of gate-all-around （GAA） silicon nanowire tunneling field effect transistors （NW-TFETs） is developted based on the surface potential solutions in the channel direction and considering the band ...An analytical model of gate-all-around （GAA） silicon nanowire tunneling field effect transistors （NW-TFETs） is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling （BTBT） efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane＇s expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.展开更多
A new analytical model to describe the drain-induced barrier lowering （DIBL） effect has been obtained by solving the two-dimensional （2D） Poisson＇s equation for the dual-channel 4H-SiC MESFET （DCFET）. Using thi...A new analytical model to describe the drain-induced barrier lowering （DIBL） effect has been obtained by solving the two-dimensional （2D） Poisson＇s equation for the dual-channel 4H-SiC MESFET （DCFET）. Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.展开更多
In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanis...In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.展开更多
Direct-current transfer characteristics of （InGaN）/A1GaN/A1N/GaN heterojunction field effect transistors （HFETs） are presented. A drain current plateau （IDs = 32.0 mA/mm） for Vcs swept from ＋0.7 V to -0. 6 V is...Direct-current transfer characteristics of （InGaN）/A1GaN/A1N/GaN heterojunction field effect transistors （HFETs） are presented. A drain current plateau （IDs = 32.0 mA/mm） for Vcs swept from ＋0.7 V to -0. 6 V is present in the transfer characteristics of InGaN/AIGaN/AIN/GaN HFETs. The theoretical calculation shows the coexistence of two-dimensional electron gas （2DEG） and two-dimensional hole gas （2DHG） in InGaN/AIGaN/A1N/GaN heterostructures, and the screening effect of 2DHG to the 2DEG in the conduction channel can explain this current plateau. Moreover, the current plateau shows the time-dependent behavior when IDs Vcs scans repeated are conducted. The obtained insight provides indication for the design in the fabrication of GaN-based super HFETs.展开更多
We report on the temperature-dependent dc performance of A1GaN/GaN polarization doped field effect transistors （PolFETs）. The rough decrements of drain current and transeonductance with the operation temperature are...We report on the temperature-dependent dc performance of A1GaN/GaN polarization doped field effect transistors （PolFETs）. The rough decrements of drain current and transeonductance with the operation temperature are observed. Compared with the conventional HFETs, the drain current drop of the PolFET is smaller. The transeonductance drop of PolFETs at different gate biases shows different temperature dependences. From the aspect of the unique carrier behaviors of graded AlGaN/GaN heterostructure, we propose a quasi-multi-channel model to investigate the physics behind the temperature-dependent performance of AlGaN/GaN PolFETs.展开更多
We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors （SB- MOSFETs） fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopa...We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors （SB- MOSFETs） fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69mV/dec. Em- phasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance Cgs with respect to Vgs at various Vds, we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each Cgs peak, the difference between Vgs and Vds is equal to the Schottky barrier height （SBH） for NiSi2 on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on chan- nel. The SBH for NiSi2 on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs.展开更多
Tunneling field effect transistors（TFETs） based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low...Tunneling field effect transistors（TFETs） based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low power devices. Here,we investigate the TFETs based on two different integration types： in-plane and vertical heterostructures composed of two kinds of layered phosphorous（β-P and δ-P） by ab initio quantum transport simulations. NDR effects have been observed in both in-plane and vertical heterostructures, and the effects become significant with the highest peak-to-valley ratio（PVR）when the intrinsic region length is near zero. Compared with the in-plane TFET based on β-P and δ-P, better performance with a higher on/off current ratio of - 10-6 and a steeper subthreshold swing（SS） of - 23 mV/dec is achieved in the vertical TFET. Such differences in the NDR effects, on/off current ratio and SS are attributed to the distinct interaction nature of theβ-P and δ-P layers in the in-plane and vertical heterostructures.展开更多
A new analytical model to describe the drain-induced barrier lowering(DIBL) effect has been obtained by solving the two-dimensional(2D) Poisson’s equation for the dual-channel 4H-SiC MESFET(DCFET).Using this analytic...A new analytical model to describe the drain-induced barrier lowering(DIBL) effect has been obtained by solving the two-dimensional(2D) Poisson’s equation for the dual-channel 4H-SiC MESFET(DCFET).Using this analytical model,we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET,which characterize the DIBL effect.The results show that they are significantly dependent on the drain bias,gate length as well as the thickness and doping concentration of the two channel layers.Based on this analytical model,the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.展开更多
A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS pro...A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.展开更多
A vertical GaN field-effect transistor with an integrated self-adapted channel diode(CD-FET)is proposed to improve the reverse conduction performance.It features a channel diode(CD)formed between a trench source on th...A vertical GaN field-effect transistor with an integrated self-adapted channel diode(CD-FET)is proposed to improve the reverse conduction performance.It features a channel diode(CD)formed between a trench source on the insulator and a P-type barrier layer(PBL),together with a P-shield layer under the trench gate.At forward conduction,the CD is pinched off due to depletion effects caused by both the PBL and the metal-insulator-semiconductor structure from the trench source,without influencing the on-state characteristic of the CD-FET.At reverse conduction,the depletion region narrows and thus the CD turns on to achieve a very low turn-on voltage(V_(F)),preventing the inherent body diode from turning on.Meanwhile,the PBL and P-shield layer can modulate the electric field distribution to improve the off-state breakdown voltage(BV).Moreover,the P-shield not only shields the gate from a high electric field but also transforms part of C_(GD)to CGS so as to significantly reduce the gate charge(Q_(GD)),leading to a low switching loss(E_(switch)).Consequently,the proposed CD-FET achieves a low V_(F)of 1.65 V and a high BV of 1446 V,and V_(F),Q_(GD)and E_(switch)of the CD-FET are decreased by 49%,55%and 80%,respectively,compared with those of a conventional metal-oxide-semiconductor field-effect transistor(MOSFET).展开更多
In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional...In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.展开更多
A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors(TFETs)is reported.The junction-less technique,in w...A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors(TFETs)is reported.The junction-less technique,in which metals with specific work functions are deposited on the source region to modulate the channel conductivity,is used to provide the necessary doping for the proper functioning of the device.TCAD simulation studies of the proposed structure and junction structure have been compared,and showed an enhanced rectification of 10^(4) times.The proposed structure is designed to have a nanocavity of length 10 nm on the left-and right-hand sides of the fixed gate dielectric,which improves the biosensor capture area,and hence the sensitivity.By considering neutral and charged biomolecules with different dielectric constants,TCAD simulation studies were compared for their sensitivities.The off-state current IOFFcan be used as a suitable sensing parameter because it has been observed that the proposed sensor exhibits a significant variation in drain current.Additionally,it has been investigated how positively and negatively charged biomolecules affect the drain current and threshold voltage.To explore the device performance when the nanogaps are fully filled,half filled and unevenly filled,extensive TCAD simulations have been run.The proposed TFET structure is further benchmarked to other structures to show its better sensing capabilities.展开更多
基金Project supported by the National Natural Science Foundation of China(Grant No.51602241)the China Postdoctoral Science Foundation(Grant No.2016M592754)
文摘In this manuscript,the perovskite-based metal–oxide–semiconductor field effect transistors（MOSFETs） with phenylC61-butyric acid methylester（PCBM） layers are studied.The MOSFETs are fabricated on perovskites,and characterized by photoluminescence spectra（PL）,x-ray diffraction（XRD）,and x-ray photoelectron spectroscopy（XPS）.With PCBM layers,the current–voltage hysteresis phenomenon is effetely inhibited,and both the transfer and output current values increase.The band energy diagrams are proposed,which indicate that the electrons are transferred into the PCBM layer,resulting in the increase of photocurrent.The electron mobility and hole mobility are extracted from the transfer curves,which are about one order of magnitude as large as those of PCBM deposited,which is the reason why the electrons are transferred into the PCBM layer and the holes are still in the perovskites,and the effects of ionized impurity scattering on carrier transport become smaller.
基金supported by Center for BioNano Health-Guardfunded by the Ministry of Science, ICT & Future Planning (MSIP) of Korea as a Global Frontier Project (HGUARD_2013M3A6B2)
文摘A facile approach was demonstrated for fabricating high-performance nonvolatile memory devices based on ferroelectric-gate field effect transistors using a p-type Si nanowire coated with omega-shaped gate organic ferroelectric poly(vinylidene fluoride-trifluoroethylene)(P(VDF-Tr FE)). We overcame the interfacial layer problem by incorporating P(VDF-Tr FE) as a ferroelectric gate using a low-temperature fabrication process. Our memory devices exhibited excellent memory characteristics with a low programming voltage of ±5 V, a large modulation in channel conductance between ON and OFF states exceeding 105, a long retention time greater than 3 9 104 s, and a high endurance of over 105 programming cycles while maintaining an ION/IOFFratio higher than 102.
基金Supported by the National Basic Research Program of China under Grant Nos 2013CB921900 and 2014CB920900the National Natural Science Foundation of China under Grant No 11374021)(S.Yan,Z.Xie,J.-H,Chen)+1 种基金support from the Elemental Strategy Initiative conducted by the MEXT,Japana Grant-in-Aid for Scientific Research on Innovative Areas"Science of Atomic Layers"from JSPS
文摘The energy bandgap is an intrinsic character of semiconductors, which largely determines their properties. The ability to continuously and reversibly tune the bandgap of a single device during real time operation is of great importance not only to device physics but also to technological applications. Here we demonstrate a widely tunable bandgap of few-layer black phosphorus （BP） by the application of vertical electric field in dual-gated BP field-effect transistors. A total bandgap reduction of 124 meV is observed when the electrical displacement field is increased from 0.10 V/nm to 0.83 V/nm. Our results suggest appealing potential for few-layer BP as a tunable bandgap material in infrared optoelectronies, thermoelectric power generation and thermal imaging.
文摘The temperature-dependent effect of residual charge carrier （no）, at the Dirac point, on mobility is studied. We fabricate and characterize a graphene field effect transistor （GFET） using 7nm TiO2 as the top-gate dielectric. The temperature-dependent gate voltage-drain current and room temperature gate capacitance are measured to extract the carrier mobility and to estimate the quantum capacitance of the GFET. The device shows the mobility value of gOO cm^2 /V.s at room temperature and it decreases to 45 cm^2 /V.s for 20 K due to the increase of n0. These results indicate that the phonon scattering is not the dominant process for the unevenness dielectric layer while the coulomb scattering by charged impurities degrades the device characteristically at low temperature.
基金supported by the National Natural Science Foundation of China(Grant Nos.51177175 and 61274039)the National Basic Research Project of China(Grant Nos.2010CB923200 and 2011CB301903)+4 种基金the Ph.D.Program Foundation of Ministry of Education of China(Grant No.20110171110021)the International Sci.&Tech.Collaboration Program of China(Grant No.2012DFG52260)the National High-tech R&D Program of China(Grant No.2014AA032606)the Science and Technology Plan of Guangdong Province,China(Grant No.2013B010401013)the Opened Fund of the State Key Laboratory on Integrated Optoelectronics(Grant No.IOSKL2014KF17)
文摘We report a novel structure of A1GaN/GaN heterostructure field effect transistors （HFETs） with a Si and Mg pair- doped interlayer grown on Si substrate. By optimizing the doping concentrations of the pair-doped interlayers, the mobility of 2DEG increases by twice for the conventional structure under 5 K due to the improved crystalline quality of the conduction channel. The proposed HFET shows a four orders lower off-state leakage current, resulting in a much higher on/off ratio （ - 10^9）. Further temperature-dependent performance of Schottky diodes revealed that the inhibition of shallow surface traps in proposed HFETs should be the main reason for the suppression of leakage current.
基金Project partly supported by National Defense Basic Research Program of China (Grant No 51327010101)
文摘Based on an analytical solution of the two-dimensional Poisson equation in the subthreshold region, this paper investigates the behavior of DIBL （drain induced barrier lowering） effect for short channel 4H-SiC metal semiconductor field effect transistors （MESFETs）. An accurate analytical model of threshold voltage shift for the asymmetric short channel 4H-SiC MESFET is presented and thus verified. According to the presented model, it analyses the threshold voltage for short channel device on the L/a （channel length/channel depth） ratio, drain applied voltage VDS and channel doping concentration ND, thus providing a good basis for the design and modelling of short channel 4H-SiC MESFETs device.
基金Project supported by the National Basic Research Program of China (Grant Nos. 2011CB808404 and 2009CB939703)the National Natural Science Foundation of China (Grant Nos. 10974074,90607022,60676001,60676008,and 60825403)
文摘This paper proposes an effective method of fabricating top contact organic field effect transistors by using a pho- tolithographic process. The semiconductor layer is protected by a passivation layer. Through photolithographic and etching processes, parts of the passivation layer are etched off to form source/drain electrode patterns. Combined with conventional evaporation and lift-off techniques, organic field effect transistors with a top contact are fabricated suc- cessfully, whose properties are comparable to those prepared with the shadow mask method and one order of magnitude higher than the bottom contact devices fabricated by using a photolithographic process.
基金supported by the National Natural Science Foundation of China(Grant Nos.11174182 and 61306113)the Specialized Research Fund for the Doctoral Program of Higher Education,China(Grant No.20110131110005)
文摘A simple and effective approach to improve the switching characteristics of AlGaN/AlN/GaN heterostructure field effect transistors （HFETs） by applying a voltage bias on the substrate is presented. With the increase of the substrate bias, the OFF-state drain current is much reduced and the ON-state current keeps constant. Both the ON/OFF current ratio and the subthreshold swing are demonstrated to be greatly improved. With the thinned substrate, the improvement of the switching characteristics with the substrate bias is found to be even greater. The above improvements of the switching characteristics are attributed to the interaction between the substrate bias induced electrical field and the bulk traps in the GaN buffer layer, which reduces the conductivity of the GaN buffer layer.
基金supported by the National Natural Science Foundation of China(Grant Nos.61274096,61204043,61306042,61306045,and 61306132)the Guangdong Natural Science Foundation,China(Grant Nos.S2012010010533 and S2013040016878)+2 种基金the Shenzhen Science&Technology Foundation,China(Grant No.ZDSY20120618161735041)the Fundamental Research Project of the Shenzhen Science&Technology Foundation,China(Grant Nos.JCYJ20120618162600041,JCYJ20120618162526384,JCYJ20130402164725025,and JCYJ20120618162946025)the International Collaboration Project of the Shenzhen Science&Technology Foundation,China(Grant Nos.GJHZ20120618162120759,GJHZ20130417170946221,GJHZ20130417170908049,and GJHZ20120615142829482)
文摘An analytical model of gate-all-around （GAA） silicon nanowire tunneling field effect transistors （NW-TFETs） is developted based on the surface potential solutions in the channel direction and considering the band to band tunneling （BTBT） efficiency. The three-dimensional Poisson equation is solved to obtain the surface potential distributions in the partition regions along the channel direction for the NW-TFET, and a tunneling current model using Kane＇s expression is developed. The validity of the developed model is shown by the good agreement between the model predictions and the TCAD simulation results.
基金Project supported by the Pre-research Foundation from the National Ministries and Commissions of China （Grant No. 51308030201）.
文摘A new analytical model to describe the drain-induced barrier lowering （DIBL） effect has been obtained by solving the two-dimensional （2D） Poisson＇s equation for the dual-channel 4H-SiC MESFET （DCFET）. Using this analytical model, we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET, which characterize the DIBL effect. The results show that they are significantly dependent on the drain bias, gate length as well as the thickness and doping concentration of the two channel layers. Based on this analytical model, the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.
基金Project supported by the National Basic Research Program of China (Grant No. 2011CBA00604)
文摘In this paper, we investigate the performance of the bulk fin field effect transistor （FinFET） through a three- dimensional （3D） full band Monte Carlo simulator with quantum correction. Several scattering mechanisms, such as the acoustic and optical phonon scattering, the ionized impurity scattering, the impact ionization scattering and the surface roughness scattering are considered in our simulator. The effects of the substrate bias and the surface roughness scattering near the Si/SiO2 interface on the performance of bulk FinFET are mainly discussed in our work. Our results show that the on-current of bulk FinFET is sensitive to the surface roughness and that we can reduce the substrate leakage current by modulating the substrate bias voltage.
基金Supported by the Knowledge Innovation Project of the Chinese Academy of Sciencesthe National Natural Science Foundation of China under Grant Nos 61204017 and 61334002+1 种基金the National Basic Research Program of Chinathe National Science and Technology Major Project of China
文摘Direct-current transfer characteristics of （InGaN）/A1GaN/A1N/GaN heterojunction field effect transistors （HFETs） are presented. A drain current plateau （IDs = 32.0 mA/mm） for Vcs swept from ＋0.7 V to -0. 6 V is present in the transfer characteristics of InGaN/AIGaN/AIN/GaN HFETs. The theoretical calculation shows the coexistence of two-dimensional electron gas （2DEG） and two-dimensional hole gas （2DHG） in InGaN/AIGaN/A1N/GaN heterostructures, and the screening effect of 2DHG to the 2DEG in the conduction channel can explain this current plateau. Moreover, the current plateau shows the time-dependent behavior when IDs Vcs scans repeated are conducted. The obtained insight provides indication for the design in the fabrication of GaN-based super HFETs.
文摘We report on the temperature-dependent dc performance of A1GaN/GaN polarization doped field effect transistors （PolFETs）. The rough decrements of drain current and transeonductance with the operation temperature are observed. Compared with the conventional HFETs, the drain current drop of the PolFET is smaller. The transeonductance drop of PolFETs at different gate biases shows different temperature dependences. From the aspect of the unique carrier behaviors of graded AlGaN/GaN heterostructure, we propose a quasi-multi-channel model to investigate the physics behind the temperature-dependent performance of AlGaN/GaN PolFETs.
基金Supported by the National Natural Science Foundation of China under Grant No 61674161the Open Project of State Key Laboratory of Functional Materials for Informatics
文摘We present an experimental analysis of Schottky-barrier metal-oxide-semiconductor field effect transistors （SB- MOSFETs） fabricated on ultrathin body silicon-on-insulator substrates with a steep junction by the dopant implantation into the silicide process. The subthreshold swing of such SB-MOSFETs reaches 69mV/dec. Em- phasis is placed on the capacitance-voltage analysis of p-type SB-MOSFETs. According to the measurements of gate-to-source capacitance Cgs with respect to Vgs at various Vds, we find that a maximum occurs at the accumulation regime due to the most imbalanced charge distribution along the channel. At each Cgs peak, the difference between Vgs and Vds is equal to the Schottky barrier height （SBH） for NiSi2 on highly doped silicon, which indicates that the critical condition of channel pinching off is related with SBH for source/drain on chan- nel. The SBH for NiSi2 on highly doped silicon can affect the pinch-off voltage and the saturation current of SB-MOSFETs.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.11604019,61574020,and 61376018)the Ministry of Science and Technology of China(Grant No.2016YFA0301300)+1 种基金the Fund of State Key Laboratory of Information Photonics and Optical Communications(Beijing University of Posts and Telecommunications),Chinathe Fundamental Research Funds for the Central Universities,China(Grant No.2016RCGD22)
文摘Tunneling field effect transistors（TFETs） based on two-dimensional materials are promising contenders to the traditional metal oxide semiconductor field effect transistor, mainly due to potential applications in low power devices. Here,we investigate the TFETs based on two different integration types： in-plane and vertical heterostructures composed of two kinds of layered phosphorous（β-P and δ-P） by ab initio quantum transport simulations. NDR effects have been observed in both in-plane and vertical heterostructures, and the effects become significant with the highest peak-to-valley ratio（PVR）when the intrinsic region length is near zero. Compared with the in-plane TFET based on β-P and δ-P, better performance with a higher on/off current ratio of - 10-6 and a steeper subthreshold swing（SS） of - 23 mV/dec is achieved in the vertical TFET. Such differences in the NDR effects, on/off current ratio and SS are attributed to the distinct interaction nature of theβ-P and δ-P layers in the in-plane and vertical heterostructures.
基金Project supported by the Pre-research Foundation from the National Ministries and Commissions of China (Grant No. 51308030201)
文摘A new analytical model to describe the drain-induced barrier lowering(DIBL) effect has been obtained by solving the two-dimensional(2D) Poisson’s equation for the dual-channel 4H-SiC MESFET(DCFET).Using this analytical model,we calculate the threshold voltage shift and the sub-threshold slope factor of the DCFET,which characterize the DIBL effect.The results show that they are significantly dependent on the drain bias,gate length as well as the thickness and doping concentration of the two channel layers.Based on this analytical model,the structure parameters of the DCFET have been optimized in order to suppress the DIBL effect and improve the performance.
基金supported by the National Natural Science Foundation of China(Grant No.61464003)the Guangxi Natural Science Foundation,China(Grant Nos.2015GXNSFAA139300 and 2018JJA170010)
文摘A stacked lateral double-diffused metal–oxide–semiconductor field-effect transistor(LDMOS) with enhanced depletion effect by surface substrate is proposed(ST-LDMOS), which is compatible with the traditional CMOS processes. The new stacked structure is characterized by double substrates and surface dielectric trenches(SDT). The drift region is separated by the P-buried layer to form two vertically parallel devices. The doping concentration of the drift region is increased benefiting from the enhanced auxiliary depletion effect of the double substrates, leading to a lower specific on-resistance(Ron,sp). Multiple electric field peaks appear at the corners of the SDT, which improves the lateral electric field distribution and the breakdown voltage(BV). Compared to a conventional LDMOS(C-LDMOS), the BV in the ST-LDMOS increases from 259 V to 459 V, an improvement of 77.22%. The Ron,sp decreases from 39.62 m?·cm^2 to 23.24 m?·cm^2 and the Baliga's figure of merit(FOM) of is 9.07 MW/cm^2.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61874149 and U20A20208)the Outstanding Youth Science and Technology Foundation of China(Grant No.2018-JCJQ-ZQ-060).
文摘A vertical GaN field-effect transistor with an integrated self-adapted channel diode(CD-FET)is proposed to improve the reverse conduction performance.It features a channel diode(CD)formed between a trench source on the insulator and a P-type barrier layer(PBL),together with a P-shield layer under the trench gate.At forward conduction,the CD is pinched off due to depletion effects caused by both the PBL and the metal-insulator-semiconductor structure from the trench source,without influencing the on-state characteristic of the CD-FET.At reverse conduction,the depletion region narrows and thus the CD turns on to achieve a very low turn-on voltage(V_(F)),preventing the inherent body diode from turning on.Meanwhile,the PBL and P-shield layer can modulate the electric field distribution to improve the off-state breakdown voltage(BV).Moreover,the P-shield not only shields the gate from a high electric field but also transforms part of C_(GD)to CGS so as to significantly reduce the gate charge(Q_(GD)),leading to a low switching loss(E_(switch)).Consequently,the proposed CD-FET achieves a low V_(F)of 1.65 V and a high BV of 1446 V,and V_(F),Q_(GD)and E_(switch)of the CD-FET are decreased by 49%,55%and 80%,respectively,compared with those of a conventional metal-oxide-semiconductor field-effect transistor(MOSFET).
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61176038 and 61474093)the Science and Technology Planning Project of Guangdong Province,China(Grant No.2015A010103002)the Technology Development Program of Shanxi Province,China(Grant No.2016GY075)
文摘In this work, a double-gate-all-around tunneling field-effect transistor is proposed. The performance of the novel device is studied by numerical simulation. The results show that with a thinner body and an additional core gate, the novel device achieves a steeper subthreshold slope, less susceptibility to the short channel effect, higher on-state current, and larger on/off current ratio than the traditional gate-all-around tunneling field-effect transistor. The excellent performance makes the proposed structure more attractive to further dimension scaling.
文摘A dielectric modulation strategy for gate oxide material that enhances the sensing performance of biosensors in junction-less vertical tunnel field effect transistors(TFETs)is reported.The junction-less technique,in which metals with specific work functions are deposited on the source region to modulate the channel conductivity,is used to provide the necessary doping for the proper functioning of the device.TCAD simulation studies of the proposed structure and junction structure have been compared,and showed an enhanced rectification of 10^(4) times.The proposed structure is designed to have a nanocavity of length 10 nm on the left-and right-hand sides of the fixed gate dielectric,which improves the biosensor capture area,and hence the sensitivity.By considering neutral and charged biomolecules with different dielectric constants,TCAD simulation studies were compared for their sensitivities.The off-state current IOFFcan be used as a suitable sensing parameter because it has been observed that the proposed sensor exhibits a significant variation in drain current.Additionally,it has been investigated how positively and negatively charged biomolecules affect the drain current and threshold voltage.To explore the device performance when the nanogaps are fully filled,half filled and unevenly filled,extensive TCAD simulations have been run.The proposed TFET structure is further benchmarked to other structures to show its better sensing capabilities.
